Lines Matching full:bit
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
76 #define TRIG_TS_INT BIT(30)
77 #define APB_TIMEOUT_INT BIT(29)
88 #define SW_SPARE_REG_2 BIT(7)
89 #define SW_SPARE_REG_1 BIT(6)
90 #define SW_SPARE_REG_0 BIT(5)
91 #define SW_BIG_ENDIAN BIT(4)
92 #define SPI_AUTO_EDGE_DETECTION BIT(1)
93 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
96 #define SW_ENABLE_REFCLKO BIT(1)
97 #define SW_REFCLKO_IS_125MHZ BIT(0)
101 #define SW_IBA_ENABLE BIT(31)
102 #define SW_IBA_DA_MATCH BIT(30)
103 #define SW_IBA_INIT BIT(29)
112 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
131 #define SW_IBA_REQ BIT(31)
132 #define SW_IBA_RESP BIT(30)
133 #define SW_IBA_DA_MISMATCH BIT(14)
134 #define SW_IBA_FMT_MISMATCH BIT(13)
135 #define SW_IBA_CODE_ERROR BIT(12)
136 #define SW_IBA_CMD_ERROR BIT(11)
137 #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
153 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
158 #define SW_PLL_POWER_DOWN BIT(5)
167 #define SW_DOUBLE_TAG BIT(7)
168 #define SW_RESET BIT(1)
169 #define SW_START BIT(0)
186 #define SW_SHAPING_CREDIT_ACCT BIT(1)
187 #define SW_POLICING_CREDIT_ACCT BIT(0)
191 #define SW_VLAN_ENABLE BIT(7)
192 #define SW_DROP_INVALID_VID BIT(6)
195 #define SW_RESV_MCAST_ENABLE BIT(2)
203 #define UNICAST_LEARN_DISABLE BIT(7)
204 #define SW_SRC_ADDR_FILTER BIT(6)
205 #define SW_FLUSH_STP_TABLE BIT(5)
206 #define SW_FLUSH_MSTP_TABLE BIT(4)
207 #define SW_FWD_MCAST_SRC_ADDR BIT(3)
208 #define SW_AGING_ENABLE BIT(2)
209 #define SW_FAST_AGING BIT(1)
210 #define SW_LINK_AUTO_AGING BIT(0)
214 #define SW_TRAP_DOUBLE_TAG BIT(6)
215 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
216 #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
233 #define LEARN_FAIL_INT BIT(2)
234 #define ALMOST_FULL_INT BIT(1)
235 #define WRITE_FAIL_INT BIT(0)
249 #define SW_UNK_UCAST_ENABLE BIT(31)
253 #define SW_UNK_MCAST_ENABLE BIT(31)
257 #define SW_UNK_VID_ENABLE BIT(31)
261 #define SW_NEW_BACKOFF BIT(7)
262 #define SW_CHECK_LENGTH BIT(3)
263 #define SW_PAUSE_UNH_MODE BIT(1)
264 #define SW_AGGR_BACKOFF BIT(0)
268 #define MULTICAST_STORM_DISABLE BIT(6)
269 #define SW_BACK_PRESSURE BIT(5)
270 #define FAIR_FLOW_CTRL BIT(4)
271 #define NO_EXC_COLLISION_DROP BIT(3)
272 #define SW_JUMBO_PACKET BIT(2)
273 #define SW_LEGAL_PACKET_DISABLE BIT(1)
274 #define SW_PASS_SHORT_FRAME BIT(0)
278 #define SW_REPLACE_VID BIT(3)
288 #define SW_PASS_PAUSE BIT(3)
292 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
296 #define SW_MIB_COUNTER_FLUSH BIT(7)
297 #define SW_MIB_COUNTER_FREEZE BIT(6)
311 #define SW_TOS_DSCP_REMARK BIT(1)
312 #define SW_TOS_DSCP_REMAP BIT(0)
349 #define SW_IGMP_SNOOP BIT(6)
350 #define SW_IPV6_MLD_OPTION BIT(3)
351 #define SW_IPV6_MLD_SNOOP BIT(2)
352 #define SW_MIRROR_RX_TX BIT(0)
356 #define SW_CLASS_D_IP_ENABLE BIT(31)
373 #define UNICAST_VLAN_BOUNDARY BIT(1)
382 #define VLAN_VALID BIT(31)
383 #define VLAN_FORWARD_OPTION BIT(27)
399 #define VLAN_START BIT(7)
412 #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
416 #define ALU_VALID_CNT_M (BIT(14) - 1)
418 #define ALU_START BIT(7)
419 #define ALU_VALID BIT(6)
420 #define ALU_DIRECT BIT(2)
428 #define ALU_STAT_INDEX_M (BIT(4) - 1)
430 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
431 #define ALU_STAT_START BIT(7)
432 #define ALU_RESV_MCAST_ADDR BIT(1)
433 #define ALU_STAT_READ BIT(0)
437 #define ALU_V_STATIC_VALID BIT(31)
438 #define ALU_V_SRC_FILTER BIT(30)
439 #define ALU_V_DST_FILTER BIT(29)
440 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
446 #define ALU_V_OVERRIDE BIT(31)
447 #define ALU_V_USE_FID BIT(30)
448 #define ALU_V_PORT_MAP (BIT(24) - 1)
452 #define ALU_V_FID_M (BIT(16) - 1)
467 #define HSR_INDEX_MAX BIT(9)
472 #define HSR_PATH_INDEX_M (BIT(4) - 1)
476 #define HSR_VALID_CNT_M (BIT(14) - 1)
478 #define HSR_START BIT(7)
479 #define HSR_VALID BIT(6)
480 #define HSR_SEARCH_END BIT(5)
481 #define HSR_DIRECT BIT(2)
489 #define HSR_V_STATIC_VALID BIT(31)
490 #define HSR_V_AGE_CNT_M (BIT(3) - 1)
492 #define HSR_V_PATH_ID_M (BIT(4) - 1)
518 #define HSR_V_SEQ_M (BIT(16) - 1)
523 #define PTP_STEP_ADJ BIT(6)
524 #define PTP_STEP_DIR BIT(5)
525 #define PTP_READ_TIME BIT(4)
526 #define PTP_LOAD_TIME BIT(3)
527 #define PTP_CLK_ADJ_ENABLE BIT(2)
528 #define PTP_CLK_ENABLE BIT(1)
529 #define PTP_CLK_RESET BIT(0)
546 #define PTP_RATE_DIR BIT(31)
547 #define PTP_TMP_RATE_ENABLE BIT(30)
557 #define PTP_802_1AS BIT(7)
558 #define PTP_ENABLE BIT(6)
559 #define PTP_ETH_ENABLE BIT(5)
560 #define PTP_IPV4_UDP_ENABLE BIT(4)
561 #define PTP_IPV6_UDP_ENABLE BIT(3)
562 #define PTP_TC_P2P BIT(2)
563 #define PTP_MASTER BIT(1)
564 #define PTP_1STEP BIT(0)
568 #define PTP_UNICAST_ENABLE BIT(12)
569 #define PTP_ALTERNATE_MASTER BIT(11)
570 #define PTP_ALL_HIGH_PRIO BIT(10)
571 #define PTP_SYNC_CHECK BIT(9)
572 #define PTP_DELAY_CHECK BIT(8)
573 #define PTP_PDELAY_CHECK BIT(7)
574 #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
575 #define PTP_DOMAIN_CHECK BIT(4)
576 #define PTP_UDP_CHECKSUM BIT(2)
605 #define GPIO_IN BIT(7)
606 #define GPIO_OUT BIT(6)
607 #define TS_INT_ENABLE BIT(5)
608 #define TRIG_ACTIVE BIT(4)
609 #define TRIG_ENABLE BIT(3)
610 #define TRIG_RESET BIT(2)
611 #define TS_ENABLE BIT(1)
612 #define TS_RESET BIT(0)
627 #define TRIG_CASCADE_ENABLE BIT(31)
628 #define TRIG_CASCADE_TAIL BIT(30)
631 #define TRIG_NOW BIT(25)
632 #define TRIG_NOTIFY BIT(24)
633 #define TRIG_EDGE BIT(23)
665 #define TS_EVENT_OVERFLOW BIT(16)
668 #define TS_DETECT_RISE BIT(7)
669 #define TS_DETECT_FALL BIT(6)
671 #define TS_CASCADE_TAIL BIT(5)
674 #define TS_CASCADE_ENABLE BIT(0)
713 #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
727 #define DLR_SRC_PORT_UNICAST BIT(31)
736 #define DLR_RESET_SEQ_ID BIT(3)
737 #define DLR_BACKUP_AUTO_ON BIT(2)
738 #define DLR_BEACON_TX_ENABLE BIT(1)
739 #define DLR_ASSIST_ENABLE BIT(0)
759 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
763 #define DLR_VLAN_ID_M (BIT(12) - 1)
783 #define HSR_DUPLICATE_DISCARD BIT(7)
784 #define HSR_NODE_UNICAST BIT(6)
787 #define HSR_LEARN_MCAST_DISABLE BIT(2)
796 #define HSR_LEARN_UCAST_DISABLE BIT(7)
797 #define HSR_FLUSH_TABLE BIT(5)
798 #define HSR_PROC_MCAST_SRC BIT(3)
799 #define HSR_AGING_ENABLE BIT(2)
808 #define HSR_WINDOW_OVERFLOW_INT BIT(3)
809 #define HSR_LEARN_FAIL_INT BIT(2)
810 #define HSR_ALMOST_FULL_INT BIT(1)
811 #define HSR_WRITE_FAIL_INT BIT(0)
815 #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
816 #define HSR_FAIL_INDEX_M (BIT(8) - 1)
820 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
824 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
839 #define PME_WOL_MAGICPKT BIT(2)
840 #define PME_WOL_LINKUP BIT(1)
841 #define PME_WOL_ENERGY BIT(0)
846 #define PORT_SGMII_INT BIT(3)
847 #define PORT_PTP_INT BIT(2)
848 #define PORT_PHY_INT BIT(1)
849 #define PORT_ACL_INT BIT(0)
856 #define PORT_MAC_LOOPBACK BIT(7)
857 #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
858 #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
859 #define PORT_TAIL_TAG_ENABLE BIT(2)
870 #define PORT_INTF_FULL_DUPLEX BIT(2)
871 #define PORT_TX_FLOW_CTRL BIT(1)
872 #define PORT_RX_FLOW_CTRL BIT(0)
879 #define PORT_PHY_RESET BIT(15)
880 #define PORT_PHY_LOOPBACK BIT(14)
881 #define PORT_SPEED_100MBIT BIT(13)
882 #define PORT_AUTO_NEG_ENABLE BIT(12)
883 #define PORT_POWER_DOWN BIT(11)
884 #define PORT_ISOLATE BIT(10)
885 #define PORT_AUTO_NEG_RESTART BIT(9)
886 #define PORT_FULL_DUPLEX BIT(8)
887 #define PORT_COLLISION_TEST BIT(7)
888 #define PORT_SPEED_1000MBIT BIT(6)
892 #define PORT_100BT4_CAPABLE BIT(15)
893 #define PORT_100BTX_FD_CAPABLE BIT(14)
894 #define PORT_100BTX_CAPABLE BIT(13)
895 #define PORT_10BT_FD_CAPABLE BIT(12)
896 #define PORT_10BT_CAPABLE BIT(11)
897 #define PORT_EXTENDED_STATUS BIT(8)
898 #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
899 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
900 #define PORT_REMOTE_FAULT BIT(4)
901 #define PORT_AUTO_NEG_CAPABLE BIT(3)
902 #define PORT_LINK_STATUS BIT(2)
903 #define PORT_JABBER_DETECT BIT(1)
904 #define PORT_EXTENDED_CAPABILITY BIT(0)
914 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
915 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
916 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
917 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
918 #define PORT_AUTO_NEG_100BT4 BIT(9)
919 #define PORT_AUTO_NEG_100BTX_FD BIT(8)
920 #define PORT_AUTO_NEG_100BTX BIT(7)
921 #define PORT_AUTO_NEG_10BT_FD BIT(6)
922 #define PORT_AUTO_NEG_10BT BIT(5)
931 #define PORT_REMOTE_NEXT_PAGE BIT(15)
932 #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
933 #define PORT_REMOTE_REMOTE_FAULT BIT(13)
934 #define PORT_REMOTE_ASYM_PAUSE BIT(11)
935 #define PORT_REMOTE_SYM_PAUSE BIT(10)
936 #define PORT_REMOTE_100BTX_FD BIT(8)
937 #define PORT_REMOTE_100BTX BIT(7)
938 #define PORT_REMOTE_10BT_FD BIT(6)
939 #define PORT_REMOTE_10BT BIT(5)
943 #define PORT_AUTO_NEG_MANUAL BIT(12)
944 #define PORT_AUTO_NEG_MASTER BIT(11)
945 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
946 #define PORT_AUTO_NEG_1000BT_FD BIT(9)
947 #define PORT_AUTO_NEG_1000BT BIT(8)
951 #define PORT_MASTER_FAULT BIT(15)
952 #define PORT_LOCAL_MASTER BIT(14)
953 #define PORT_LOCAL_RX_OK BIT(13)
954 #define PORT_REMOTE_RX_OK BIT(12)
955 #define PORT_REMOTE_1000BT_FD BIT(11)
956 #define PORT_REMOTE_1000BT BIT(10)
987 #define DSP_SQI_ERR_DETECTED BIT(15)
995 #define EEE_ADV_100MBIT BIT(1)
996 #define EEE_ADV_1GBIT BIT(2)
1005 #define PORT_100BTX_FD_ABLE BIT(15)
1006 #define PORT_100BTX_ABLE BIT(14)
1007 #define PORT_10BT_FD_ABLE BIT(13)
1008 #define PORT_10BT_ABLE BIT(12)
1011 #define PORT_SGMII_AUTO_INCR BIT(23)
1014 #define PORT_SGMII_ADDR_M (BIT(21) - 1)
1017 #define PORT_SGMII_DATA_M (BIT(16) - 1)
1031 #define SR_MII_RESET BIT(15)
1032 #define SR_MII_LOOPBACK BIT(14)
1033 #define SR_MII_SPEED_100MBIT BIT(13)
1034 #define SR_MII_AUTO_NEG_ENABLE BIT(12)
1035 #define SR_MII_POWER_DOWN BIT(11)
1036 #define SR_MII_AUTO_NEG_RESTART BIT(9)
1037 #define SR_MII_FULL_DUPLEX BIT(8)
1038 #define SR_MII_SPEED_1000MBIT BIT(6)
1045 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1058 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1059 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1069 #define SR_MII_8_BIT BIT(8)
1070 #define SR_MII_SGMII_LINK_UP BIT(4)
1071 #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1075 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1079 #define SR_MII_STAT_LINK_UP BIT(4)
1085 #define SR_MII_STAT_FULL_DUPLEX BIT(1)
1091 #define SR_MII_PHY_WRITE BIT(1)
1092 #define SR_MII_PHY_START_BUSY BIT(0)
1096 #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1100 #define SR_MII_PHY_DATA_M (BIT(16) - 1)
1107 #define PORT_REMOTE_LOOPBACK BIT(8)
1110 #define PORT_LED_CTRL_TEST BIT(3)
1111 #define PORT_10BT_PREAMBLE BIT(2)
1112 #define PORT_LINK_MD_10BT_ENABLE BIT(1)
1113 #define PORT_LINK_MD_PASS BIT(0)
1117 #define PORT_START_CABLE_DIAG BIT(15)
1118 #define PORT_TX_DISABLE BIT(14)
1133 #define PORT_1000_LINK_GOOD BIT(1)
1134 #define PORT_100_LINK_GOOD BIT(0)
1138 #define PORT_LINK_DETECT BIT(14)
1139 #define PORT_SIGNAL_DETECT BIT(13)
1140 #define PORT_PHY_STAT_MDI BIT(12)
1141 #define PORT_PHY_STAT_MASTER BIT(11)
1148 #define JABBER_INT BIT(7)
1149 #define RX_ERR_INT BIT(6)
1150 #define PAGE_RX_INT BIT(5)
1151 #define PARALLEL_DETECT_FAULT_INT BIT(4)
1152 #define LINK_PARTNER_ACK_INT BIT(3)
1153 #define LINK_DOWN_INT BIT(2)
1154 #define REMOTE_FAULT_INT BIT(1)
1155 #define LINK_UP_INT BIT(0)
1159 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1160 #define PORT_PHY_FORCE_MDI BIT(7)
1161 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1164 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1170 #define PORT_100BT_FIXED_LATENCY BIT(15)
1174 #define PORT_INT_PIN_HIGH BIT(14)
1175 #define PORT_ENABLE_JABBER BIT(9)
1176 #define PORT_STAT_SPEED_1000MBIT BIT(6)
1177 #define PORT_STAT_SPEED_100MBIT BIT(5)
1178 #define PORT_STAT_SPEED_10MBIT BIT(4)
1179 #define PORT_STAT_FULL_DUPLEX BIT(3)
1182 #define PORT_STAT_MASTER BIT(2)
1183 #define PORT_RESET BIT(1)
1184 #define PORT_LINK_STATUS_FAIL BIT(0)
1189 #define PORT_SGMII_SEL BIT(7)
1190 #define PORT_MII_FULL_DUPLEX BIT(6)
1191 #define PORT_MII_100MBIT BIT(4)
1192 #define PORT_GRXC_ENABLE BIT(0)
1196 #define PORT_RMII_CLK_SEL BIT(7)
1198 #define PORT_MII_1000MBIT_S1 BIT(6)
1200 #define PORT_MII_NOT_1GBIT BIT(6)
1201 #define PORT_MII_SEL_EDGE BIT(5)
1202 #define PORT_RGMII_ID_IG_ENABLE BIT(4)
1203 #define PORT_RGMII_ID_EG_ENABLE BIT(3)
1204 #define PORT_MII_MAC_MODE BIT(2)
1220 #define PORT_BROADCAST_STORM BIT(1)
1221 #define PORT_JUMBO_FRAME BIT(0)
1225 #define PORT_BACK_PRESSURE BIT(3)
1226 #define PORT_PASS_ALL BIT(0)
1230 #define PORT_100BT_EEE_DISABLE BIT(7)
1231 #define PORT_1000BT_EEE_DISABLE BIT(6)
1240 #define PORT_IN_PORT_BASED BIT(6)
1241 #define PORT_IN_PACKET_BASED BIT(5)
1242 #define PORT_IN_FLOW_CTRL BIT(4)
1249 #define PORT_COUNT_IFG BIT(1)
1250 #define PORT_COUNT_PREAMBLE BIT(0)
1266 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
1271 #define MIB_COUNTER_OVERFLOW BIT(31)
1272 #define MIB_COUNTER_VALID BIT(30)
1273 #define MIB_COUNTER_READ BIT(25)
1274 #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1275 #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1306 #define ACL_SRC BIT(1)
1307 #define ACL_EQUAL BIT(0)
1333 #define ACL_TCP_FLAG_ENABLE BIT(0)
1355 #define ACL_VLAN_PRIO_REPLACE BIT(2)
1370 #define ACL_CNT_M (BIT(11) - 1)
1376 #define ACL_MSEC_UNIT BIT(6)
1377 #define ACL_INTR_MODE BIT(5)
1400 #define PORT_ACL_WRITE_DONE BIT(6)
1401 #define PORT_ACL_READ_DONE BIT(5)
1402 #define PORT_ACL_WRITE BIT(4)
1410 #define PORT_MIRROR_RX BIT(6)
1411 #define PORT_MIRROR_TX BIT(5)
1412 #define PORT_MIRROR_SNIFFER BIT(1)
1416 #define PORT_HIGHEST_PRIO BIT(7)
1417 #define PORT_OR_PRIO BIT(6)
1418 #define PORT_MAC_PRIO_ENABLE BIT(4)
1419 #define PORT_VLAN_PRIO_ENABLE BIT(3)
1420 #define PORT_802_1P_PRIO_ENABLE BIT(2)
1421 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1422 #define PORT_ACL_PRIO_ENABLE BIT(0)
1426 #define PORT_USER_PRIO_CEILING BIT(7)
1427 #define PORT_DROP_NON_VLAN BIT(4)
1428 #define PORT_DROP_TAG BIT(3)
1434 #define PORT_ACL_ENABLE BIT(2)
1454 #define POLICE_DROP_ALL BIT(10)
1461 #define PORT_BASED_POLICING BIT(7)
1464 #define COLOR_MARK_ENABLE BIT(4)
1465 #define COLOR_REMAP_ENABLE BIT(3)
1466 #define POLICE_DROP_SRP BIT(2)
1467 #define POLICE_COLOR_NOT_AWARE BIT(1)
1468 #define POLICE_ENABLE BIT(0)
1476 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1491 #define WRED_PM_CTRL_M (BIT(11) - 1)
1506 #define WRED_RANDOM_DROP_ENABLE BIT(31)
1507 #define WRED_PMON_FLUSH BIT(30)
1508 #define WRED_DROP_GYR_DISABLE BIT(29)
1509 #define WRED_DROP_YR_DISABLE BIT(28)
1510 #define WRED_DROP_R_DISABLE BIT(27)
1511 #define WRED_DROP_ALL BIT(26)
1512 #define WRED_PMON_M (BIT(24) - 1)
1520 #define MTI_PVID_REPLACE BIT(0)
1536 #define MTI_TX_RATIO_M (BIT(7) - 1)
1557 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1563 #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1568 #define PORT_QM_TX_CNT_M (BIT(11) - 1)
1578 #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1579 #define PORT_INGRESS_FILTER BIT(6)
1580 #define PORT_DISCARD_NON_VID BIT(5)
1581 #define PORT_MAC_BASED_802_1X BIT(4)
1582 #define PORT_SRC_ADDR_FILTER BIT(3)
1588 #define PORT_TX_ENABLE BIT(2)
1589 #define PORT_RX_ENABLE BIT(1)
1590 #define PORT_LEARN_DISABLE BIT(0)
1613 #define PTP_PORT_SYNC_INT BIT(15)
1614 #define PTP_PORT_XDELAY_REQ_INT BIT(14)
1615 #define PTP_PORT_PDELAY_RESP_INT BIT(13)
1656 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1657 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)