Lines Matching refs:cdev
324 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) in m_can_read() argument
326 return cdev->ops->read_reg(cdev, reg); in m_can_read()
329 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, in m_can_write() argument
332 cdev->ops->write_reg(cdev, reg, val); in m_can_write()
335 static u32 m_can_fifo_read(struct m_can_classdev *cdev, in m_can_fifo_read() argument
338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read()
341 return cdev->ops->read_fifo(cdev, addr_offset); in m_can_fifo_read()
344 static void m_can_fifo_write(struct m_can_classdev *cdev, in m_can_fifo_write() argument
347 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write()
350 cdev->ops->write_fifo(cdev, addr_offset, val); in m_can_fifo_write()
353 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev, in m_can_fifo_write_no_off() argument
356 cdev->ops->write_fifo(cdev, fpi, val); in m_can_fifo_write_no_off()
359 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset) in m_can_txe_fifo_read() argument
361 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + in m_can_txe_fifo_read()
364 return cdev->ops->read_fifo(cdev, addr_offset); in m_can_txe_fifo_read()
367 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) in m_can_tx_fifo_full() argument
369 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); in m_can_tx_fifo_full()
372 void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) in m_can_config_endisable() argument
374 u32 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_config_endisable()
388 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); in m_can_config_endisable()
391 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); in m_can_config_endisable()
393 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); in m_can_config_endisable()
400 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { in m_can_config_endisable()
402 netdev_warn(cdev->net, "Failed to init module\n"); in m_can_config_endisable()
410 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) in m_can_enable_all_interrupts() argument
413 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); in m_can_enable_all_interrupts()
416 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) in m_can_disable_all_interrupts() argument
418 m_can_write(cdev, M_CAN_ILE, 0x0); in m_can_disable_all_interrupts()
423 struct m_can_classdev *cdev = netdev_priv(net); in m_can_clean() local
425 if (cdev->tx_skb) { in m_can_clean()
429 if (cdev->version > 30) in m_can_clean()
430 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & in m_can_clean()
433 can_free_echo_skb(cdev->net, putidx); in m_can_clean()
434 cdev->tx_skb = NULL; in m_can_clean()
441 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_read_fifo() local
449 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC); in m_can_read_fifo()
464 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID); in m_can_read_fifo()
483 m_can_fifo_read(cdev, fgi, in m_can_read_fifo()
488 m_can_write(cdev, M_CAN_RXF0A, fgi); in m_can_read_fifo()
498 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_do_rx_poll() local
502 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
516 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
551 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lec_err() local
556 cdev->can.can_stats.bus_error++; in m_can_handle_lec_err()
608 struct m_can_classdev *cdev = netdev_priv(dev); in __m_can_get_berr_counter() local
611 ecr = m_can_read(cdev, M_CAN_ECR); in __m_can_get_berr_counter()
618 static int m_can_clk_start(struct m_can_classdev *cdev) in m_can_clk_start() argument
622 if (cdev->pm_clock_support == 0) in m_can_clk_start()
625 err = pm_runtime_get_sync(cdev->dev); in m_can_clk_start()
627 pm_runtime_put_noidle(cdev->dev); in m_can_clk_start()
634 static void m_can_clk_stop(struct m_can_classdev *cdev) in m_can_clk_stop() argument
636 if (cdev->pm_clock_support) in m_can_clk_stop()
637 pm_runtime_put_sync(cdev->dev); in m_can_clk_stop()
643 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_get_berr_counter() local
646 err = m_can_clk_start(cdev); in m_can_get_berr_counter()
652 m_can_clk_stop(cdev); in m_can_get_berr_counter()
660 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_change() local
670 cdev->can.can_stats.error_warning++; in m_can_handle_state_change()
671 cdev->can.state = CAN_STATE_ERROR_WARNING; in m_can_handle_state_change()
675 cdev->can.can_stats.error_passive++; in m_can_handle_state_change()
676 cdev->can.state = CAN_STATE_ERROR_PASSIVE; in m_can_handle_state_change()
680 cdev->can.state = CAN_STATE_BUS_OFF; in m_can_handle_state_change()
681 m_can_disable_all_interrupts(cdev); in m_can_handle_state_change()
682 cdev->can.can_stats.bus_off++; in m_can_handle_state_change()
709 ecr = m_can_read(cdev, M_CAN_ECR); in m_can_handle_state_change()
734 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_errors() local
737 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { in m_can_handle_state_errors()
743 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { in m_can_handle_state_errors()
749 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { in m_can_handle_state_errors()
789 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_protocol_error() local
800 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { in m_can_handle_protocol_error()
802 cdev->can.can_stats.arbitration_lost++; in m_can_handle_protocol_error()
821 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_bus_errors() local
828 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
833 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
845 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_handler() local
849 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); in m_can_rx_handler()
863 if (cdev->version <= 31 && irqstatus & IR_MRAF && in m_can_rx_handler()
864 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { in m_can_rx_handler()
869 m_can_write(cdev, M_CAN_IR, IR_MRAF); in m_can_rx_handler()
874 psr = m_can_read(cdev, M_CAN_PSR); in m_can_rx_handler()
890 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_peripheral() local
894 m_can_enable_all_interrupts(cdev); in m_can_rx_peripheral()
902 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_poll() local
908 m_can_enable_all_interrupts(cdev); in m_can_poll()
922 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_echo_tx_event() local
926 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); in m_can_echo_tx_event()
935 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) in m_can_echo_tx_event()
939 msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) & in m_can_echo_tx_event()
943 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK & in m_can_echo_tx_event()
955 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_isr() local
959 if (pm_runtime_suspended(cdev->dev)) in m_can_isr()
961 ir = m_can_read(cdev, M_CAN_IR); in m_can_isr()
967 m_can_write(cdev, M_CAN_IR, ir); in m_can_isr()
969 if (cdev->ops->clear_interrupts) in m_can_isr()
970 cdev->ops->clear_interrupts(cdev); in m_can_isr()
978 cdev->irqstatus = ir; in m_can_isr()
979 m_can_disable_all_interrupts(cdev); in m_can_isr()
980 if (!cdev->is_peripheral) in m_can_isr()
981 napi_schedule(&cdev->napi); in m_can_isr()
986 if (cdev->version == 30) { in m_can_isr()
1000 !m_can_tx_fifo_full(cdev)) in m_can_isr()
1058 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_set_bittiming() local
1059 const struct can_bittiming *bt = &cdev->can.bittiming; in m_can_set_bittiming()
1060 const struct can_bittiming *dbt = &cdev->can.data_bittiming; in m_can_set_bittiming()
1070 m_can_write(cdev, M_CAN_NBTP, reg_btp); in m_can_set_bittiming()
1072 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_set_bittiming()
1094 tdco = (cdev->can.clock.freq / 1000) * in m_can_set_bittiming()
1105 m_can_write(cdev, M_CAN_TDCR, in m_can_set_bittiming()
1114 m_can_write(cdev, M_CAN_DBTP, reg_btp); in m_can_set_bittiming()
1131 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_chip_config() local
1134 m_can_config_endisable(cdev, true); in m_can_chip_config()
1137 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); in m_can_chip_config()
1140 m_can_write(cdev, M_CAN_GFC, 0x0); in m_can_chip_config()
1142 if (cdev->version == 30) { in m_can_chip_config()
1144 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | in m_can_chip_config()
1145 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1148 m_can_write(cdev, M_CAN_TXBC, in m_can_chip_config()
1149 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | in m_can_chip_config()
1150 (cdev->mcfg[MRAM_TXB].off)); in m_can_chip_config()
1154 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); in m_can_chip_config()
1157 if (cdev->version == 30) { in m_can_chip_config()
1158 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | in m_can_chip_config()
1159 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1162 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1163 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) in m_can_chip_config()
1165 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1169 m_can_write(cdev, M_CAN_RXF0C, in m_can_chip_config()
1170 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | in m_can_chip_config()
1171 cdev->mcfg[MRAM_RXF0].off); in m_can_chip_config()
1173 m_can_write(cdev, M_CAN_RXF1C, in m_can_chip_config()
1174 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | in m_can_chip_config()
1175 cdev->mcfg[MRAM_RXF1].off); in m_can_chip_config()
1177 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_chip_config()
1178 test = m_can_read(cdev, M_CAN_TEST); in m_can_chip_config()
1180 if (cdev->version == 30) { in m_can_chip_config()
1187 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1196 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) in m_can_chip_config()
1199 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1204 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in m_can_chip_config()
1210 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in m_can_chip_config()
1214 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) in m_can_chip_config()
1218 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_chip_config()
1219 m_can_write(cdev, M_CAN_TEST, test); in m_can_chip_config()
1222 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); in m_can_chip_config()
1223 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) in m_can_chip_config()
1224 if (cdev->version == 30) in m_can_chip_config()
1225 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & in m_can_chip_config()
1228 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & in m_can_chip_config()
1231 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); in m_can_chip_config()
1234 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); in m_can_chip_config()
1239 m_can_config_endisable(cdev, false); in m_can_chip_config()
1241 if (cdev->ops->init) in m_can_chip_config()
1242 cdev->ops->init(cdev); in m_can_chip_config()
1247 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start() local
1252 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_start()
1254 m_can_enable_all_interrupts(cdev); in m_can_start()
1277 static int m_can_check_core_release(struct m_can_classdev *cdev) in m_can_check_core_release() argument
1287 crel_reg = m_can_read(cdev, M_CAN_CREL); in m_can_check_core_release()
1305 static bool m_can_niso_supported(struct m_can_classdev *cdev) in m_can_niso_supported() argument
1311 m_can_config_endisable(cdev, true); in m_can_niso_supported()
1312 cccr_reg = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1314 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1317 cccr_poll = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1328 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1330 m_can_config_endisable(cdev, false); in m_can_niso_supported()
1416 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_stop() local
1419 m_can_disable_all_interrupts(cdev); in m_can_stop()
1422 m_can_config_endisable(cdev, true); in m_can_stop()
1425 cdev->can.state = CAN_STATE_STOPPED; in m_can_stop()
1430 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_close() local
1434 if (!cdev->is_peripheral) in m_can_close()
1435 napi_disable(&cdev->napi); in m_can_close()
1438 m_can_clk_stop(cdev); in m_can_close()
1441 if (cdev->is_peripheral) { in m_can_close()
1442 cdev->tx_skb = NULL; in m_can_close()
1443 destroy_workqueue(cdev->tx_wq); in m_can_close()
1444 cdev->tx_wq = NULL; in m_can_close()
1455 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_next_echo_skb_occupied() local
1457 unsigned int wrap = cdev->can.echo_skb_max; in m_can_next_echo_skb_occupied()
1464 return !!cdev->can.echo_skb[next_idx]; in m_can_next_echo_skb_occupied()
1467 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) in m_can_tx_handler() argument
1469 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; in m_can_tx_handler()
1470 struct net_device *dev = cdev->net; in m_can_tx_handler()
1471 struct sk_buff *skb = cdev->tx_skb; in m_can_tx_handler()
1488 if (cdev->version == 30) { in m_can_tx_handler()
1492 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id); in m_can_tx_handler()
1493 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC, in m_can_tx_handler()
1497 m_can_fifo_write(cdev, 0, in m_can_tx_handler()
1503 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_tx_handler()
1504 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_tx_handler()
1516 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_tx_handler()
1518 m_can_write(cdev, M_CAN_TXBTIE, 0x1); in m_can_tx_handler()
1519 m_can_write(cdev, M_CAN_TXBAR, 0x1); in m_can_tx_handler()
1525 if (m_can_tx_fifo_full(cdev)) { in m_can_tx_handler()
1531 if (cdev->is_peripheral) { in m_can_tx_handler()
1541 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) in m_can_tx_handler()
1544 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); in m_can_tx_handler()
1559 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, in m_can_tx_handler()
1566 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4), in m_can_tx_handler()
1575 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); in m_can_tx_handler()
1578 if (m_can_tx_fifo_full(cdev) || in m_can_tx_handler()
1588 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, in m_can_tx_work_queue() local
1591 m_can_tx_handler(cdev); in m_can_tx_work_queue()
1592 cdev->tx_skb = NULL; in m_can_tx_work_queue()
1598 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start_xmit() local
1603 if (cdev->is_peripheral) { in m_can_start_xmit()
1604 if (cdev->tx_skb) { in m_can_start_xmit()
1609 if (cdev->can.state == CAN_STATE_BUS_OFF) { in m_can_start_xmit()
1617 cdev->tx_skb = skb; in m_can_start_xmit()
1618 netif_stop_queue(cdev->net); in m_can_start_xmit()
1619 queue_work(cdev->tx_wq, &cdev->tx_work); in m_can_start_xmit()
1622 cdev->tx_skb = skb; in m_can_start_xmit()
1623 return m_can_tx_handler(cdev); in m_can_start_xmit()
1631 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_open() local
1634 err = m_can_clk_start(cdev); in m_can_open()
1646 if (cdev->is_peripheral) { in m_can_open()
1647 cdev->tx_skb = NULL; in m_can_open()
1648 cdev->tx_wq = alloc_workqueue("mcan_wq", in m_can_open()
1650 if (!cdev->tx_wq) { in m_can_open()
1655 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); in m_can_open()
1675 if (!cdev->is_peripheral) in m_can_open()
1676 napi_enable(&cdev->napi); in m_can_open()
1683 if (cdev->is_peripheral) in m_can_open()
1684 destroy_workqueue(cdev->tx_wq); in m_can_open()
1688 m_can_clk_stop(cdev); in m_can_open()
1707 static void m_can_of_parse_mram(struct m_can_classdev *cdev, in m_can_of_parse_mram() argument
1710 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; in m_can_of_parse_mram()
1711 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; in m_can_of_parse_mram()
1712 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + in m_can_of_parse_mram()
1713 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1714 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; in m_can_of_parse_mram()
1715 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + in m_can_of_parse_mram()
1716 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1717 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & in m_can_of_parse_mram()
1719 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + in m_can_of_parse_mram()
1720 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; in m_can_of_parse_mram()
1721 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & in m_can_of_parse_mram()
1723 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + in m_can_of_parse_mram()
1724 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; in m_can_of_parse_mram()
1725 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; in m_can_of_parse_mram()
1726 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + in m_can_of_parse_mram()
1727 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; in m_can_of_parse_mram()
1728 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; in m_can_of_parse_mram()
1729 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + in m_can_of_parse_mram()
1730 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; in m_can_of_parse_mram()
1731 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & in m_can_of_parse_mram()
1734 dev_dbg(cdev->dev, in m_can_of_parse_mram()
1736 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, in m_can_of_parse_mram()
1737 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, in m_can_of_parse_mram()
1738 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, in m_can_of_parse_mram()
1739 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, in m_can_of_parse_mram()
1740 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, in m_can_of_parse_mram()
1741 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, in m_can_of_parse_mram()
1742 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); in m_can_of_parse_mram()
1745 void m_can_init_ram(struct m_can_classdev *cdev) in m_can_init_ram() argument
1752 start = cdev->mcfg[MRAM_SIDF].off; in m_can_init_ram()
1753 end = cdev->mcfg[MRAM_TXB].off + in m_can_init_ram()
1754 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_init_ram()
1757 m_can_fifo_write_no_off(cdev, i, 0x0); in m_can_init_ram()
1875 struct m_can_classdev *cdev = netdev_priv(ndev); in m_can_class_suspend() local
1881 m_can_clk_stop(cdev); in m_can_class_suspend()
1886 cdev->can.state = CAN_STATE_SLEEPING; in m_can_class_suspend()
1895 struct m_can_classdev *cdev = netdev_priv(ndev); in m_can_class_resume() local
1899 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_class_resume()
1904 ret = m_can_clk_start(cdev); in m_can_class_resume()
1908 m_can_init_ram(cdev); in m_can_class_resume()