1217 		u32 reg_fdcbt, reg_ctrl2;  in flexcan_set_bittiming_cbt()  local
1253 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_set_bittiming_cbt()
1254 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1256 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1258 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);  in flexcan_set_bittiming_cbt()
1259 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_set_bittiming_cbt()
1322 	u32 reg_ctrl2;  in flexcan_ram_init()  local
1332 	reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_ram_init()
1333 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1334 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1345 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1346 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1358 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;  in flexcan_chip_start()  local
1465 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1466 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;  in flexcan_chip_start()
1467 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1546 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1547 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1548 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1566 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1567 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()