Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
2 * Toshiba TMIO NAND flash controller driver
4 * Slightly murky pre-git history of the driver:
7 * Original work, independent of sharps code. Included hardware ECC support.
8 * Hard ECC did not work for writes in the early revisions.
42 /*--------------------------------------------------------------------------*/
45 * NAND Flash Host Controller Configuration Register
48 #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
53 #define CCR_ECCC 0x5b /* b ECC Control */
54 #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
55 #define CCR_NFM 0x61 /* b NAND Flash Monitor */
56 #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
57 #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
60 * NAND Flash Control Register
63 #define FCR_MODE 0x04 /* b Mode Register */
73 #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
74 #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
75 #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
103 /*--------------------------------------------------------------------------*/
129 /*--------------------------------------------------------------------------*/
137 u8 mode; in tmio_nand_hwcontrol() local
140 mode = FCR_MODE_DATA; in tmio_nand_hwcontrol()
143 mode |= FCR_MODE_CLE; in tmio_nand_hwcontrol()
145 mode &= ~FCR_MODE_CLE; in tmio_nand_hwcontrol()
148 mode |= FCR_MODE_ALE; in tmio_nand_hwcontrol()
150 mode &= ~FCR_MODE_ALE; in tmio_nand_hwcontrol()
152 mode = FCR_MODE_STANDBY; in tmio_nand_hwcontrol()
155 tmio_iowrite8(mode, tmio->fcr + FCR_MODE); in tmio_nand_hwcontrol()
156 tmio->read_good = 0; in tmio_nand_hwcontrol()
160 tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W); in tmio_nand_hwcontrol()
167 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); in tmio_nand_dev_ready()
175 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_irq()
176 complete(&tmio->comp); in tmio_irq()
195 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); in tmio_nand_wait()
196 reinit_completion(&tmio->comp); in tmio_nand_wait()
197 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); in tmio_nand_wait()
200 timeout = wait_for_completion_timeout(&tmio->comp, in tmio_nand_wait()
204 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
205 dev_warn(&tmio->dev->dev, "still busy after 400 ms\n"); in tmio_nand_wait()
208 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
209 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); in tmio_nand_wait()
217 *The TMIO controller combines two 8-bit data bytes into one 16-bit
222 *tmio->read_good.
229 if (tmio->read_good--) in tmio_nand_read_byte()
230 return tmio->read; in tmio_nand_read_byte()
232 data = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_read_byte()
233 tmio->read = data >> 8; in tmio_nand_read_byte()
238 *The TMIO controller converts an 8-bit NAND interface to a 16-bit
239 *bus interface, so all data reads and writes must be 16-bit wide.
240 *Thus, we implement 16-bit versions of the read, write, and verify
248 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); in tmio_nand_write_buf()
255 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); in tmio_nand_read_buf()
258 static void tmio_nand_enable_hwecc(struct nand_chip *chip, int mode) in tmio_nand_enable_hwecc() argument
262 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); in tmio_nand_enable_hwecc()
263 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ in tmio_nand_enable_hwecc()
264 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); in tmio_nand_enable_hwecc()
271 unsigned int ecc; in tmio_nand_calculate_ecc() local
273 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); in tmio_nand_calculate_ecc()
275 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
276 ecc_code[1] = ecc; /* 000-255 LP7-0 */ in tmio_nand_calculate_ecc()
277 ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ in tmio_nand_calculate_ecc()
278 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
279 ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ in tmio_nand_calculate_ecc()
280 ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ in tmio_nand_calculate_ecc()
281 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
282 ecc_code[3] = ecc; /* 256-511 LP15-8 */ in tmio_nand_calculate_ecc()
283 ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ in tmio_nand_calculate_ecc()
285 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); in tmio_nand_calculate_ecc()
295 /* assume ecc.size = 512 and ecc.bytes = 6 */ in tmio_nand_correct_data()
311 if (cell->enable) { in tmio_hw_init()
312 ret = cell->enable(dev); in tmio_hw_init()
318 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); in tmio_hw_init()
321 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); in tmio_hw_init()
322 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); in tmio_hw_init()
325 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); in tmio_hw_init()
328 /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ in tmio_hw_init()
329 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); in tmio_hw_init()
332 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); in tmio_hw_init()
335 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); in tmio_hw_init()
338 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); in tmio_hw_init()
339 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); in tmio_hw_init()
340 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); in tmio_hw_init()
342 /* Standby Mode smode */ in tmio_hw_init()
343 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); in tmio_hw_init()
354 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); in tmio_hw_stop()
355 if (cell->disable) in tmio_hw_stop()
356 cell->disable(dev); in tmio_hw_stop()
361 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in tmio_attach_chip()
364 chip->ecc.size = 512; in tmio_attach_chip()
365 chip->ecc.bytes = 6; in tmio_attach_chip()
366 chip->ecc.strength = 2; in tmio_attach_chip()
367 chip->ecc.hwctl = tmio_nand_enable_hwecc; in tmio_attach_chip()
368 chip->ecc.calculate = tmio_nand_calculate_ecc; in tmio_attach_chip()
369 chip->ecc.correct = tmio_nand_correct_data; in tmio_attach_chip()
380 struct tmio_nand_data *data = dev_get_platdata(&dev->dev); in tmio_probe()
392 dev_warn(&dev->dev, "NULL platform data!\n"); in tmio_probe()
394 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL); in tmio_probe()
396 return -ENOMEM; in tmio_probe()
398 init_completion(&tmio->comp); in tmio_probe()
400 tmio->dev = dev; in tmio_probe()
403 nand_chip = &tmio->chip; in tmio_probe()
405 mtd->name = "tmio-nand"; in tmio_probe()
406 mtd->dev.parent = &dev->dev; in tmio_probe()
408 nand_controller_init(&tmio->controller); in tmio_probe()
409 tmio->controller.ops = &tmio_ops; in tmio_probe()
410 nand_chip->controller = &tmio->controller; in tmio_probe()
412 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr)); in tmio_probe()
413 if (!tmio->ccr) in tmio_probe()
414 return -EIO; in tmio_probe()
416 tmio->fcr_base = fcr->start & 0xfffff; in tmio_probe()
417 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr)); in tmio_probe()
418 if (!tmio->fcr) in tmio_probe()
419 return -EIO; in tmio_probe()
425 /* Set address of NAND IO lines */ in tmio_probe()
426 nand_chip->legacy.IO_ADDR_R = tmio->fcr; in tmio_probe()
427 nand_chip->legacy.IO_ADDR_W = tmio->fcr; in tmio_probe()
430 nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol; in tmio_probe()
431 nand_chip->legacy.dev_ready = tmio_nand_dev_ready; in tmio_probe()
432 nand_chip->legacy.read_byte = tmio_nand_read_byte; in tmio_probe()
433 nand_chip->legacy.write_buf = tmio_nand_write_buf; in tmio_probe()
434 nand_chip->legacy.read_buf = tmio_nand_read_buf; in tmio_probe()
437 nand_chip->badblock_pattern = data->badblock_pattern; in tmio_probe()
440 nand_chip->legacy.chip_delay = 15; in tmio_probe()
442 retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0, in tmio_probe()
443 dev_name(&dev->dev), tmio); in tmio_probe()
445 dev_err(&dev->dev, "request_irq error %d\n", retval); in tmio_probe()
449 tmio->irq = irq; in tmio_probe()
450 nand_chip->legacy.waitfunc = tmio_nand_wait; in tmio_probe()
459 data ? data->part_parsers : NULL, in tmio_probe()
461 data ? data->partition : NULL, in tmio_probe()
462 data ? data->num_partitions : 0); in tmio_probe()
476 struct nand_chip *chip = &tmio->chip; in tmio_remove()
491 if (cell->suspend) in tmio_suspend()
492 cell->suspend(dev); in tmio_suspend()
502 /* FIXME - is this required or merely another attack of the broken in tmio_resume()
507 if (cell->resume) in tmio_resume()
508 cell->resume(dev); in tmio_resume()
518 .driver.name = "tmio-nand",
530 MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
531 MODULE_ALIAS("platform:tmio-nand");