Lines Matching +full:nand +full:- +full:no +full:- +full:ecc +full:- +full:engine
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
71 /* physical DMA address - 32 bit value*/
77 #define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
79 #define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */
87 #define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */
89 #define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */
93 /* ECC syndrome format - read from reg #0 will return two copies of these for
97 #define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */
109 struct nand_chip *chip; /* nand chip backpointer */
120 int dma_stage; /* 0 - idle, 1 - first step,
121 2 - second step */