Lines Matching refs:nandc
183 #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ argument
184 nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
193 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
473 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
475 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
477 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
482 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
486 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
495 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
518 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
520 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
522 if (!nandc->props->is_bam) in clear_bam_transaction()
536 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
538 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
574 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
576 return ioread32(nandc->base + offset); in nandc_read()
579 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
582 iowrite32(val, nandc->base + offset); in nandc_write()
585 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
588 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
592 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
594 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
597 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
599 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
649 static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, in nandc_set_reg() argument
652 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
665 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in set_address() local
670 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); in set_address()
671 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); in set_address()
684 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
710 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd); in update_rw_regs()
711 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
712 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); in update_rw_regs()
713 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg); in update_rw_regs()
714 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
715 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
716 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
717 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in update_rw_regs()
720 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? in update_rw_regs()
729 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
737 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
745 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
751 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
766 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
768 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
780 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
781 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
789 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
794 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
808 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
815 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
823 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
825 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
829 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
848 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
863 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
868 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
884 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
894 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
921 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
932 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
933 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
936 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
937 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
940 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
942 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
946 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
948 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
955 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
972 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
978 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
979 nandc->reg_read_pos += num_regs; in read_reg_dma()
982 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
984 if (nandc->props->is_bam) in read_reg_dma()
985 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
991 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1003 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1007 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1023 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1026 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1028 if (nandc->props->is_bam) in write_reg_dma()
1029 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1035 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1048 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1051 if (nandc->props->is_bam) in read_data_dma()
1052 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1054 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1066 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1069 if (nandc->props->is_bam) in write_data_dma()
1070 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1072 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1079 static void config_nand_page_read(struct qcom_nand_controller *nandc) in config_nand_page_read() argument
1081 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1082 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1083 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1084 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1085 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1094 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc) in config_nand_cw_read() argument
1096 if (nandc->props->is_bam) in config_nand_cw_read()
1097 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, in config_nand_cw_read()
1100 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1101 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1104 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1105 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1108 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1117 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc, in config_nand_single_cw_page_read() argument
1120 config_nand_page_read(nandc); in config_nand_single_cw_page_read()
1121 config_nand_cw_read(nandc, use_ecc); in config_nand_single_cw_page_read()
1128 static void config_nand_page_write(struct qcom_nand_controller *nandc) in config_nand_page_write() argument
1130 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1131 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1132 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1140 static void config_nand_cw_write(struct qcom_nand_controller *nandc) in config_nand_cw_write() argument
1142 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1143 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1145 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1147 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1148 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1160 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_param() local
1167 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE); in nandc_param()
1168 nandc_set_reg(nandc, NAND_ADDR0, 0); in nandc_param()
1169 nandc_set_reg(nandc, NAND_ADDR1, 0); in nandc_param()
1170 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE in nandc_param()
1174 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES in nandc_param()
1181 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); in nandc_param()
1184 nandc_set_reg(nandc, NAND_DEV_CMD_VLD, in nandc_param()
1185 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1186 nandc_set_reg(nandc, NAND_DEV_CMD1, in nandc_param()
1187 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1190 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in nandc_param()
1192 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1193 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1194 nandc_set_read_loc(nandc, 0, 0, 512, 1); in nandc_param()
1196 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in nandc_param()
1197 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1199 nandc->buf_count = 512; in nandc_param()
1200 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1202 config_nand_single_cw_page_read(nandc, false); in nandc_param()
1204 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1205 nandc->buf_count, 0); in nandc_param()
1208 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in nandc_param()
1209 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1218 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in erase_block() local
1220 nandc_set_reg(nandc, NAND_FLASH_CMD, in erase_block()
1222 nandc_set_reg(nandc, NAND_ADDR0, page_addr); in erase_block()
1223 nandc_set_reg(nandc, NAND_ADDR1, 0); in erase_block()
1224 nandc_set_reg(nandc, NAND_DEV0_CFG0, in erase_block()
1226 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1227 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in erase_block()
1228 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1229 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1231 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in erase_block()
1232 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in erase_block()
1233 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in erase_block()
1235 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1237 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in erase_block()
1238 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1247 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_id() local
1252 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID); in read_id()
1253 nandc_set_reg(nandc, NAND_ADDR0, column); in read_id()
1254 nandc_set_reg(nandc, NAND_ADDR1, 0); in read_id()
1255 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, in read_id()
1256 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1257 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in read_id()
1259 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in read_id()
1260 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in read_id()
1262 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in read_id()
1271 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in reset() local
1273 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE); in reset()
1274 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in reset()
1276 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1277 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1279 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in reset()
1285 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1289 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1292 if (nandc->props->is_bam) { in submit_descs()
1294 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1300 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1307 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1314 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1317 if (nandc->props->is_bam) { in submit_descs()
1326 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1327 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1328 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1334 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1341 static void free_descs(struct qcom_nand_controller *nandc) in free_descs() argument
1345 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1348 if (nandc->props->is_bam) in free_descs()
1349 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1352 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1360 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1362 nandc->reg_read_pos = 0; in clear_read_regs()
1363 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1369 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in pre_command() local
1371 nandc->buf_count = 0; in pre_command()
1372 nandc->buf_start = 0; in pre_command()
1376 clear_read_regs(nandc); in pre_command()
1380 clear_bam_transaction(nandc); in pre_command()
1391 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_erase_write_errors() local
1397 nandc_read_buffer_sync(nandc, true); in parse_erase_write_errors()
1400 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1415 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in post_command() local
1419 nandc_read_buffer_sync(nandc, true); in post_command()
1420 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1421 nandc->buf_count); in post_command()
1443 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_command() local
1456 nandc->buf_count = 4; in qcom_nandc_command()
1493 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1495 free_descs(nandc); in qcom_nandc_command()
1500 ret = submit_descs(nandc); in qcom_nandc_command()
1502 dev_err(nandc->dev, in qcom_nandc_command()
1507 free_descs(nandc); in qcom_nandc_command()
1570 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1574 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1589 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1597 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1600 config_nand_page_read(nandc); in qcom_nandc_read_cw_raw()
1615 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1616 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); in qcom_nandc_read_cw_raw()
1619 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); in qcom_nandc_read_cw_raw()
1622 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); in qcom_nandc_read_cw_raw()
1625 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); in qcom_nandc_read_cw_raw()
1628 config_nand_cw_read(nandc, false); in qcom_nandc_read_cw_raw()
1630 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1633 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1636 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1639 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1641 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1642 free_descs(nandc); in qcom_nandc_read_cw_raw()
1644 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1730 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1739 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1740 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1834 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1839 config_nand_page_read(nandc); in read_page_ecc()
1854 if (nandc->props->is_bam) { in read_page_ecc()
1856 nandc_set_read_loc(nandc, 0, 0, data_size, 0); in read_page_ecc()
1857 nandc_set_read_loc(nandc, 1, data_size, in read_page_ecc()
1860 nandc_set_read_loc(nandc, 0, 0, data_size, 1); in read_page_ecc()
1862 nandc_set_read_loc(nandc, 0, data_size, in read_page_ecc()
1867 config_nand_cw_read(nandc, true); in read_page_ecc()
1870 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1886 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1896 ret = submit_descs(nandc); in read_page_ecc()
1897 free_descs(nandc); in read_page_ecc()
1900 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1914 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
1919 clear_read_regs(nandc); in copy_last_cw()
1924 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1929 config_nand_single_cw_page_read(nandc, host->use_ecc); in copy_last_cw()
1931 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1933 ret = submit_descs(nandc); in copy_last_cw()
1935 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1937 free_descs(nandc); in copy_last_cw()
1947 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
1954 clear_bam_transaction(nandc); in qcom_nandc_read_page()
1986 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
1989 clear_read_regs(nandc); in qcom_nandc_read_oob()
1990 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
2004 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
2011 clear_read_regs(nandc); in qcom_nandc_write_page()
2012 clear_bam_transaction(nandc); in qcom_nandc_write_page()
2019 config_nand_page_write(nandc); in qcom_nandc_write_page()
2034 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2047 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2051 config_nand_cw_write(nandc); in qcom_nandc_write_page()
2057 ret = submit_descs(nandc); in qcom_nandc_write_page()
2059 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2061 free_descs(nandc); in qcom_nandc_write_page()
2076 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2082 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2083 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2090 config_nand_page_write(nandc); in qcom_nandc_write_page_raw()
2109 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2114 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2119 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2124 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2127 config_nand_cw_write(nandc); in qcom_nandc_write_page_raw()
2130 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2132 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2134 free_descs(nandc); in qcom_nandc_write_page_raw()
2153 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2160 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2166 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2168 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2174 config_nand_page_write(nandc); in qcom_nandc_write_oob()
2175 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2176 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2177 config_nand_cw_write(nandc); in qcom_nandc_write_oob()
2179 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2181 free_descs(nandc); in qcom_nandc_write_oob()
2184 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2195 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2209 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2215 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2221 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2224 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2232 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2236 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2237 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2244 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2253 config_nand_page_write(nandc); in qcom_nandc_block_markbad()
2254 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2255 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2256 config_nand_cw_write(nandc); in qcom_nandc_block_markbad()
2258 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2260 free_descs(nandc); in qcom_nandc_block_markbad()
2263 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2279 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_byte() local
2280 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2291 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2292 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2299 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_buf() local
2300 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2302 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2303 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2309 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_buf() local
2310 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2312 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2314 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2320 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_select_chip() local
2325 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2469 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2486 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2510 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2557 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2615 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2617 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2620 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2633 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
2635 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2636 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2637 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2639 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2642 if (nandc->tx_chan) in qcom_nandc_unalloc()
2643 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2645 if (nandc->rx_chan) in qcom_nandc_unalloc()
2646 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2648 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2649 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2651 if (nandc->chan) in qcom_nandc_unalloc()
2652 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2656 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
2660 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2662 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2672 nandc->buf_size = 532; in qcom_nandc_alloc()
2674 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2676 if (!nandc->data_buffer) in qcom_nandc_alloc()
2679 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2681 if (!nandc->regs) in qcom_nandc_alloc()
2684 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2685 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2687 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2690 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2691 nandc->reg_read_dma = in qcom_nandc_alloc()
2692 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2694 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2696 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2697 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2701 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
2702 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
2703 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
2704 nandc->tx_chan = NULL; in qcom_nandc_alloc()
2705 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2710 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
2711 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
2712 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
2713 nandc->rx_chan = NULL; in qcom_nandc_alloc()
2714 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2719 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
2720 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
2721 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
2722 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
2723 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2734 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2735 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2736 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2737 dev_err(nandc->dev, in qcom_nandc_alloc()
2743 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2744 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
2745 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
2746 nandc->chan = NULL; in qcom_nandc_alloc()
2747 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2753 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2754 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2756 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2757 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2761 qcom_nandc_unalloc(nandc); in qcom_nandc_alloc()
2766 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
2771 if (!nandc->props->is_qpic) in qcom_nandc_setup()
2772 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
2773 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
2777 if (nandc->props->is_bam) { in qcom_nandc_setup()
2778 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
2788 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
2790 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
2794 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2795 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2800 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
2806 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2842 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2853 if (nandc->props->is_bam) { in qcom_nand_host_init_and_register()
2854 free_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2855 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2856 if (!nandc->bam_txn) { in qcom_nand_host_init_and_register()
2857 dev_err(nandc->dev, in qcom_nand_host_init_and_register()
2870 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
2872 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2884 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
2890 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2893 if (list_empty(&nandc->host_list)) in qcom_probe_nand_devices()
2902 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
2903 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2906 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
2908 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2910 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2915 &nandc->data_crci); in qcom_nandc_parse_dt()
2917 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2927 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
2933 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
2934 if (!nandc) in qcom_nandc_probe()
2937 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
2938 nandc->dev = dev; in qcom_nandc_probe()
2946 nandc->props = dev_data; in qcom_nandc_probe()
2948 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2949 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2950 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2952 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2953 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2954 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2961 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
2962 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2963 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2965 nandc->base_phys = res->start; in qcom_nandc_probe()
2966 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2969 if (!nandc->base_dma) in qcom_nandc_probe()
2972 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
2976 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2980 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2984 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
2988 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
2995 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2997 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
2999 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
3009 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
3015 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3022 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
3024 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3025 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3027 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()