Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
144 /* NAND OP_CMDs */
163 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
177 /* ECC modes supported by the controller */
193 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
195 /* Returns the NAND register physical address */
196 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
200 ((chip)->reg_read_dma + \
201 ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
227 * NAND transfers.
228 * @bam_ce - the array of BAM command elements
229 * @cmd_sgl - sgl for NAND BAM command pipe
230 * @data_sgl - sgl for NAND BAM consumer/producer pipe
231 * @bam_ce_pos - the index in bam_ce which is available for next sgl
232 * @bam_ce_start - the index in bam_ce which marks the start position ce
235 * @cmd_sgl_pos - current index in command sgl.
236 * @cmd_sgl_start - start index in command sgl.
237 * @tx_sgl_pos - current index in data sgl for tx.
238 * @tx_sgl_start - start index in data sgl for tx.
239 * @rx_sgl_pos - current index in data sgl for rx.
240 * @rx_sgl_start - start index in data sgl for rx.
241 * @wait_second_completion - wait for second DMA desc completion before making
242 * the NAND transfer completion.
243 * @txn_done - completion for NAND transfer.
244 * @last_data_desc - last DMA desc in data channel (tx/rx).
245 * @last_cmd_desc - last DMA desc in command channel.
266 * This data type corresponds to the nand dma descriptor
267 * @list - list for desc_info
268 * @dir - DMA transfer direction
269 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
271 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
272 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
273 * @dma_desc - low level DMA engine descriptor
324 * NAND controller data struct
344 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
354 * @props: properties of current NAND controller,
357 * from all connected NAND devices pagesize
408 * NAND chip structure
410 * @chip: base NAND chip structure
416 * of a page, consisting of all data, ecc, spare
419 * by ECC
420 * @use_ecc: request the controller to use ECC for the
422 * @bch_enabled: flag to tell whether BCH ECC mode is used
423 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
431 * ecc/non-ecc mode for the current nand flash
458 * This data type corresponds to the NAND controller properties which varies
459 * among different NAND controllers.
460 * @ecc_modes - ecc mode for NAND
461 * @is_bam - whether NAND controller is using BAM
462 * @is_qpic - whether NAND CTRL is part of qpic IP
463 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
475 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
477 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
486 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
491 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + in alloc_bam_transaction()
492 (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + in alloc_bam_transaction()
493 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); in alloc_bam_transaction()
495 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
502 bam_txn->bam_ce = bam_txn_buf; in alloc_bam_transaction()
504 sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw; in alloc_bam_transaction()
506 bam_txn->cmd_sgl = bam_txn_buf; in alloc_bam_transaction()
508 sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw; in alloc_bam_transaction()
510 bam_txn->data_sgl = bam_txn_buf; in alloc_bam_transaction()
512 init_completion(&bam_txn->txn_done); in alloc_bam_transaction()
520 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
522 if (!nandc->props->is_bam) in clear_bam_transaction()
525 bam_txn->bam_ce_pos = 0; in clear_bam_transaction()
526 bam_txn->bam_ce_start = 0; in clear_bam_transaction()
527 bam_txn->cmd_sgl_pos = 0; in clear_bam_transaction()
528 bam_txn->cmd_sgl_start = 0; in clear_bam_transaction()
529 bam_txn->tx_sgl_pos = 0; in clear_bam_transaction()
530 bam_txn->tx_sgl_start = 0; in clear_bam_transaction()
531 bam_txn->rx_sgl_pos = 0; in clear_bam_transaction()
532 bam_txn->rx_sgl_start = 0; in clear_bam_transaction()
533 bam_txn->last_data_desc = NULL; in clear_bam_transaction()
534 bam_txn->wait_second_completion = false; in clear_bam_transaction()
536 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
538 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
541 reinit_completion(&bam_txn->txn_done); in clear_bam_transaction()
550 * In case of data transfer with NAND, 2 callbacks will be generated. in qpic_bam_dma_done()
556 if (bam_txn->wait_second_completion) in qpic_bam_dma_done()
557 bam_txn->wait_second_completion = false; in qpic_bam_dma_done()
559 complete(&bam_txn->txn_done); in qpic_bam_dma_done()
570 return container_of(chip->controller, struct qcom_nand_controller, in get_qcom_nand_controller()
576 return ioread32(nandc->base + offset); in nandc_read()
582 iowrite32(val, nandc->base + offset); in nandc_write()
588 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
592 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
594 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
597 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
599 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
607 return ®s->cmd; in offset_to_nandc_reg()
609 return ®s->addr0; in offset_to_nandc_reg()
611 return ®s->addr1; in offset_to_nandc_reg()
613 return ®s->chip_sel; in offset_to_nandc_reg()
615 return ®s->exec; in offset_to_nandc_reg()
617 return ®s->clrflashstatus; in offset_to_nandc_reg()
619 return ®s->cfg0; in offset_to_nandc_reg()
621 return ®s->cfg1; in offset_to_nandc_reg()
623 return ®s->ecc_bch_cfg; in offset_to_nandc_reg()
625 return ®s->clrreadstatus; in offset_to_nandc_reg()
627 return ®s->cmd1; in offset_to_nandc_reg()
629 return ®s->orig_cmd1; in offset_to_nandc_reg()
631 return ®s->vld; in offset_to_nandc_reg()
633 return ®s->orig_vld; in offset_to_nandc_reg()
635 return ®s->ecc_buf_cfg; in offset_to_nandc_reg()
637 return ®s->read_location0; in offset_to_nandc_reg()
639 return ®s->read_location1; in offset_to_nandc_reg()
641 return ®s->read_location2; in offset_to_nandc_reg()
643 return ®s->read_location3; in offset_to_nandc_reg()
652 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
664 struct nand_chip *chip = &host->chip; in set_address()
667 if (chip->options & NAND_BUSWIDTH_16) in set_address()
676 * written to the NAND controller registers via DMA
683 struct nand_chip *chip = &host->chip; in update_rw_regs()
688 if (host->use_ecc) in update_rw_regs()
696 if (host->use_ecc) { in update_rw_regs()
697 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
698 (num_cw - 1) << CW_PER_PAGE; in update_rw_regs()
700 cfg1 = host->cfg1; in update_rw_regs()
701 ecc_bch_cfg = host->ecc_bch_cfg; in update_rw_regs()
703 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
704 (num_cw - 1) << CW_PER_PAGE; in update_rw_regs()
706 cfg1 = host->cfg1_raw; in update_rw_regs()
714 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
715 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
716 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
720 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? in update_rw_regs()
721 host->cw_data : host->cw_size, 1); in update_rw_regs()
726 * for BAM. This descriptor will be added in the NAND DMA descriptor queue
727 * which will be submitted to DMA engine.
737 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
743 return -ENOMEM; in prepare_bam_async_desc()
745 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
746 sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start]; in prepare_bam_async_desc()
747 sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start; in prepare_bam_async_desc()
748 bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos; in prepare_bam_async_desc()
750 desc->dir = DMA_TO_DEVICE; in prepare_bam_async_desc()
751 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
752 sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start]; in prepare_bam_async_desc()
753 sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start; in prepare_bam_async_desc()
754 bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos; in prepare_bam_async_desc()
756 desc->dir = DMA_TO_DEVICE; in prepare_bam_async_desc()
758 sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start]; in prepare_bam_async_desc()
759 sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start; in prepare_bam_async_desc()
760 bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos; in prepare_bam_async_desc()
762 desc->dir = DMA_FROM_DEVICE; in prepare_bam_async_desc()
765 sg_mark_end(sgl + sgl_cnt - 1); in prepare_bam_async_desc()
766 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
768 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
770 return -ENOMEM; in prepare_bam_async_desc()
773 desc->sgl_cnt = sgl_cnt; in prepare_bam_async_desc()
774 desc->bam_sgl = sgl; in prepare_bam_async_desc()
780 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
781 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
783 return -EINVAL; in prepare_bam_async_desc()
786 desc->dma_desc = dma_desc; in prepare_bam_async_desc()
789 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
790 bam_txn->last_cmd_desc = dma_desc; in prepare_bam_async_desc()
792 bam_txn->last_data_desc = dma_desc; in prepare_bam_async_desc()
794 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
800 * Prepares the command descriptor for BAM DMA which will be used for NAND
815 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
817 bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos]; in prep_bam_dma_desc_cmd()
834 bam_txn->bam_ce_pos += size; in prep_bam_dma_desc_cmd()
838 bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start]; in prep_bam_dma_desc_cmd()
839 bam_ce_size = (bam_txn->bam_ce_pos - in prep_bam_dma_desc_cmd()
840 bam_txn->bam_ce_start) * in prep_bam_dma_desc_cmd()
842 sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos], in prep_bam_dma_desc_cmd()
844 bam_txn->cmd_sgl_pos++; in prep_bam_dma_desc_cmd()
845 bam_txn->bam_ce_start = bam_txn->bam_ce_pos; in prep_bam_dma_desc_cmd()
848 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
860 * Prepares the data descriptor for BAM DMA which will be used for NAND
868 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
871 sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos], in prep_bam_dma_desc_data()
873 bam_txn->rx_sgl_pos++; in prep_bam_dma_desc_data()
875 sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos], in prep_bam_dma_desc_data()
877 bam_txn->tx_sgl_pos++; in prep_bam_dma_desc_data()
884 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
907 return -ENOMEM; in prep_adm_dma_desc()
909 sgl = &desc->adm_sgl; in prep_adm_dma_desc()
915 desc->dir = DMA_FROM_DEVICE; in prep_adm_dma_desc()
918 desc->dir = DMA_TO_DEVICE; in prep_adm_dma_desc()
921 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
923 ret = -ENOMEM; in prep_adm_dma_desc()
932 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
933 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
936 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
937 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
940 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
942 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
946 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
948 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
949 ret = -EINVAL; in prep_adm_dma_desc()
953 desc->dma_desc = dma_desc; in prep_adm_dma_desc()
955 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
978 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
979 nandc->reg_read_pos += num_regs; in read_reg_dma()
984 if (nandc->props->is_bam) in read_reg_dma()
1007 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1014 vaddr = ®s->erased_cw_detect_cfg_set; in write_reg_dma()
1016 vaddr = ®s->erased_cw_detect_cfg_clr; in write_reg_dma()
1028 if (nandc->props->is_bam) in write_reg_dma()
1051 if (nandc->props->is_bam) in read_data_dma()
1069 if (nandc->props->is_bam) in write_data_dma()
1077 * before reading a NAND page.
1091 * before reading each codeword in NAND page.
1096 if (nandc->props->is_bam) in config_nand_cw_read()
1126 * before writing a NAND page.
1138 * before writing each codeword in NAND page.
1152 * the following functions are used within chip->legacy.cmdfunc() to
1159 struct nand_chip *chip = &host->chip; in nandc_param()
1185 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1187 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1192 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1193 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1199 nandc->buf_count = 512; in nandc_param()
1200 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1204 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1205 nandc->buf_count, 0); in nandc_param()
1217 struct nand_chip *chip = &host->chip; in erase_block()
1225 host->cfg0_raw & ~(7 << CW_PER_PAGE)); in erase_block()
1226 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1228 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1229 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1246 struct nand_chip *chip = &host->chip; in read_id()
1249 if (column == -1) in read_id()
1256 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1270 struct nand_chip *chip = &host->chip; in reset()
1289 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1292 if (nandc->props->is_bam) { in submit_descs()
1293 if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { in submit_descs()
1294 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1299 if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { in submit_descs()
1300 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1306 if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { in submit_descs()
1307 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1314 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1315 cookie = dmaengine_submit(desc->dma_desc); in submit_descs()
1317 if (nandc->props->is_bam) { in submit_descs()
1318 bam_txn->last_cmd_desc->callback = qpic_bam_dma_done; in submit_descs()
1319 bam_txn->last_cmd_desc->callback_param = bam_txn; in submit_descs()
1320 if (bam_txn->last_data_desc) { in submit_descs()
1321 bam_txn->last_data_desc->callback = qpic_bam_dma_done; in submit_descs()
1322 bam_txn->last_data_desc->callback_param = bam_txn; in submit_descs()
1323 bam_txn->wait_second_completion = true; in submit_descs()
1326 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1327 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1328 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1330 if (!wait_for_completion_timeout(&bam_txn->txn_done, in submit_descs()
1332 return -ETIMEDOUT; in submit_descs()
1334 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1335 return -ETIMEDOUT; in submit_descs()
1345 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1346 list_del(&desc->node); in free_descs()
1348 if (nandc->props->is_bam) in free_descs()
1349 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1350 desc->sgl_cnt, desc->dir); in free_descs()
1352 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1353 desc->dir); in free_descs()
1359 /* reset the register read buffer for next NAND operation */
1362 nandc->reg_read_pos = 0; in clear_read_regs()
1368 struct nand_chip *chip = &host->chip; in pre_command()
1371 nandc->buf_count = 0; in pre_command()
1372 nandc->buf_start = 0; in pre_command()
1373 host->use_ecc = false; in pre_command()
1374 host->last_command = command; in pre_command()
1390 struct nand_chip *chip = &host->chip; in parse_erase_write_errors()
1392 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors() local
1396 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; in parse_erase_write_errors()
1400 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1403 host->status &= ~NAND_STATUS_WP; in parse_erase_write_errors()
1405 if (flash_status & FS_OP_ERR || (i == (num_cw - 1) && in parse_erase_write_errors()
1408 host->status |= NAND_STATUS_FAIL; in parse_erase_write_errors()
1414 struct nand_chip *chip = &host->chip; in post_command()
1420 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1421 nandc->buf_count); in post_command()
1433 * Implements chip->legacy.cmdfunc. It's only used for a limited set of
1442 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_command() local
1456 nandc->buf_count = 4; in qcom_nandc_command()
1475 host->use_ecc = true; in qcom_nandc_command()
1477 update_rw_regs(host, ecc->steps, true); in qcom_nandc_command()
1493 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1502 dev_err(nandc->dev, in qcom_nandc_command()
1513 * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1516 * when using RS ECC, the HW reports the same erros when reading an erased CW,
1520 * verify if the page is erased or not, and fix up the page for RS ECC by
1569 struct nand_chip *chip = &host->chip; in check_flash_errors()
1574 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1577 return -EIO; in check_flash_errors()
1590 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw() local
1595 host->use_ecc = false; in qcom_nandc_read_cw_raw()
1598 set_address(host, host->cw_size * cw, page); in qcom_nandc_read_cw_raw()
1602 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
1603 oob_size1 = host->bbm_size; in qcom_nandc_read_cw_raw()
1605 if (cw == (ecc->steps - 1)) { in qcom_nandc_read_cw_raw()
1606 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
1607 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
1608 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
1609 host->spare_bytes; in qcom_nandc_read_cw_raw()
1611 data_size2 = host->cw_data - data_size1; in qcom_nandc_read_cw_raw()
1612 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_read_cw_raw()
1615 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1644 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1653 * number of 0 in each CW for which ECC engine returns the uncorrectable
1655 * equal to the ecc->strength for each CW.
1658 * top-level API can be called with only data buf or OOB buf so use
1659 * chip->data_buf if data buf is null and chip->oob_poi if oob buf
1663 * The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1671 struct nand_chip *chip = &host->chip; in check_for_erased_page()
1673 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page() local
1682 oob_buf = chip->oob_poi; in check_for_erased_page()
1685 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
1686 if (cw == (ecc->steps - 1)) { in check_for_erased_page()
1687 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
1688 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
1690 data_size = host->cw_data; in check_for_erased_page()
1691 oob_size = host->ecc_bytes_hw; in check_for_erased_page()
1695 cw_data_buf = data_buf + (cw * host->cw_data); in check_for_erased_page()
1696 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
1705 * as not-erased by HW because of a few bitflips in check_for_erased_page()
1708 cw_oob_buf + host->bbm_size, in check_for_erased_page()
1710 0, ecc->strength); in check_for_erased_page()
1712 mtd->ecc_stats.failed++; in check_for_erased_page()
1714 mtd->ecc_stats.corrected += ret; in check_for_erased_page()
1724 * errors. this is equivalent to what 'ecc->correct()' would do.
1729 struct nand_chip *chip = &host->chip; in parse_read_errors()
1732 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors() local
1739 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1742 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
1746 if (i == (ecc->steps - 1)) { in parse_read_errors()
1747 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
1748 oob_len = ecc->steps << 2; in parse_read_errors()
1750 data_len = host->cw_data; in parse_read_errors()
1754 flash = le32_to_cpu(buf->flash); in parse_read_errors()
1755 buffer = le32_to_cpu(buf->buffer); in parse_read_errors()
1756 erased_cw = le32_to_cpu(buf->erased_cw); in parse_read_errors()
1759 * Check ECC failure for each codeword. ECC failure can in parse_read_errors()
1761 * 1. If number of bitflips are greater than ECC engine in parse_read_errors()
1768 * For BCH ECC, ignore erased codeword errors, if in parse_read_errors()
1771 if (host->bch_enabled) { in parse_read_errors()
1775 * For RS ECC, HW reports the erased CW by placing in parse_read_errors()
1798 * No ECC or operational errors happened. Check the number of in parse_read_errors()
1805 mtd->ecc_stats.corrected += stat; in parse_read_errors()
1812 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
1816 return -EIO; in parse_read_errors()
1827 * helper to perform the actual page read operation, used by ecc->read_page(),
1828 * ecc->read_oob()
1833 struct nand_chip *chip = &host->chip; in read_page_ecc()
1835 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc() local
1842 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
1845 if (i == (ecc->steps - 1)) { in read_page_ecc()
1846 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
1847 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
1848 host->spare_bytes; in read_page_ecc()
1850 data_size = host->cw_data; in read_page_ecc()
1851 oob_size = host->ecc_bytes_hw + host->spare_bytes; in read_page_ecc()
1854 if (nandc->props->is_bam) { in read_page_ecc()
1874 * when ecc is enabled, the controller doesn't read the real in read_page_ecc()
1876 * consistent layout across RAW and ECC reads, we just in read_page_ecc()
1883 for (j = 0; j < host->bbm_size; j++) in read_page_ecc()
1900 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1913 struct nand_chip *chip = &host->chip; in copy_last_cw()
1915 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw() local
1921 size = host->use_ecc ? host->cw_data : host->cw_size; in copy_last_cw()
1924 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1926 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
1929 config_nand_single_cw_page_read(nandc, host->use_ecc); in copy_last_cw()
1931 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1935 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1942 /* implements ecc->read_page() */
1952 oob_buf = oob_required ? chip->oob_poi : NULL; in qcom_nandc_read_page()
1959 /* implements ecc->read_page_raw() */
1965 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw() local
1967 u8 *data_buf = buf, *oob_buf = chip->oob_poi; in qcom_nandc_read_page_raw()
1969 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
1975 data_buf += host->cw_data; in qcom_nandc_read_page_raw()
1976 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
1982 /* implements ecc->read_oob() */
1987 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob() local
1992 host->use_ecc = true; in qcom_nandc_read_oob()
1994 update_rw_regs(host, ecc->steps, true); in qcom_nandc_read_oob()
1996 return read_page_ecc(host, NULL, chip->oob_poi, page); in qcom_nandc_read_oob()
1999 /* implements ecc->write_page() */
2005 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page() local
2015 oob_buf = chip->oob_poi; in qcom_nandc_write_page()
2017 host->use_ecc = true; in qcom_nandc_write_page()
2018 update_rw_regs(host, ecc->steps, false); in qcom_nandc_write_page()
2021 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
2024 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page()
2025 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
2026 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
2027 host->spare_bytes; in qcom_nandc_write_page()
2029 data_size = host->cw_data; in qcom_nandc_write_page()
2030 oob_size = ecc->bytes; in qcom_nandc_write_page()
2035 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
2038 * when ECC is enabled, we don't really need to write anything in qcom_nandc_write_page()
2039 * to oob for the first n - 1 codewords since these oob regions in qcom_nandc_write_page()
2040 * just contain ECC bytes that's written by the controller in qcom_nandc_write_page()
2044 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page()
2045 oob_buf += host->bbm_size; in qcom_nandc_write_page()
2059 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2069 /* implements ecc->write_page_raw() */
2077 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw() local
2086 oob_buf = chip->oob_poi; in qcom_nandc_write_page_raw()
2088 host->use_ecc = false; in qcom_nandc_write_page_raw()
2089 update_rw_regs(host, ecc->steps, false); in qcom_nandc_write_page_raw()
2092 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
2096 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
2097 oob_size1 = host->bbm_size; in qcom_nandc_write_page_raw()
2099 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page_raw()
2100 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
2101 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
2102 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
2103 host->spare_bytes; in qcom_nandc_write_page_raw()
2105 data_size2 = host->cw_data - data_size1; in qcom_nandc_write_page_raw()
2106 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_write_page_raw()
2132 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2143 * implements ecc->write_oob()
2145 * the NAND controller cannot write only data or only OOB within a codeword
2146 * since ECC is calculated for the combined codeword. So update the OOB from
2147 * chip->oob_poi, and pad the data area with OxFF before writing.
2154 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob() local
2155 u8 *oob = chip->oob_poi; in qcom_nandc_write_oob()
2159 host->use_ecc = true; in qcom_nandc_write_oob()
2163 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
2164 oob_size = mtd->oobavail; in qcom_nandc_write_oob()
2166 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2168 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2169 0, mtd->oobavail); in qcom_nandc_write_oob()
2171 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
2176 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2184 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2185 return -EIO; in qcom_nandc_write_oob()
2196 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad() local
2199 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_bad()
2203 * the beginning of the last codeword, we don't care about reading ecc in qcom_nandc_block_bad()
2207 host->use_ecc = false; in qcom_nandc_block_bad()
2215 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2219 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
2221 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2223 if (chip->options & NAND_BUSWIDTH_16) in qcom_nandc_block_bad()
2224 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2233 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad() local
2244 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2246 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_markbad()
2249 host->use_ecc = false; in qcom_nandc_block_markbad()
2250 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
2255 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2263 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2264 return -EIO; in qcom_nandc_block_markbad()
2271 * the three functions below implement chip->legacy.read_byte(),
2272 * chip->legacy.read_buf() and chip->legacy.write_buf() respectively. these
2280 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2283 if (host->last_command == NAND_CMD_STATUS) { in qcom_nandc_read_byte()
2284 ret = host->status; in qcom_nandc_read_byte()
2286 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_nandc_read_byte()
2291 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2292 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2300 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2302 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2303 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2310 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2312 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2314 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2325 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2329 * NAND controller page layout info
2331 * Layout with ECC enabled:
2333 * |----------------------| |---------------------------------|
2335 * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
2336 * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy|
2338 * |----------------------| |---------------------------------|
2339 * codeword 1,2..n-1 codeword n
2340 * <---(528/532 Bytes)--> <-------(528/532 Bytes)--------->
2343 * . = ECC bytes
2352 * the qcom nand controller operates at a sub page/codeword level. each
2353 * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2354 * the number of ECC bytes vary based on the ECC strength and the bus width.
2356 * the first n - 1 codewords contains 516 bytes of user data, the remaining
2357 * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2360 * When we access a page with ECC enabled, the reserved bytes(s) are not
2365 * Layout with ECC disabled:
2367 * |------------------------------| |---------------------------------------|
2369 * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
2372 * |------------------------------| |---------------------------------------|
2373 * codeword 1,2..n-1 codeword n
2374 * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)----------->
2377 * . = ECC bytes
2384 * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2385 * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
2388 * In order to have a consistent layout between RAW and ECC modes, we assume
2391 * |-----------| |--------------------|
2393 * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
2396 * |-----------| |--------------------|
2397 * first n - 1 nth OOB region
2401 * . = ECC bytes
2403 * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2405 * b = Real bad block byte(s) (inaccessible when ECC enabled)
2407 * This layout is read as is when ECC is disabled. When ECC is enabled, the
2409 * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2410 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2418 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc() local
2421 return -ERANGE; in qcom_nand_ooblayout_ecc()
2424 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
2425 host->bbm_size; in qcom_nand_ooblayout_ecc()
2426 oobregion->offset = 0; in qcom_nand_ooblayout_ecc()
2428 oobregion->length = host->ecc_bytes_hw + host->spare_bytes; in qcom_nand_ooblayout_ecc()
2429 oobregion->offset = mtd->oobsize - oobregion->length; in qcom_nand_ooblayout_ecc()
2440 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free() local
2443 return -ERANGE; in qcom_nand_ooblayout_free()
2445 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
2446 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
2452 .ecc = qcom_nand_ooblayout_ecc,
2468 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip() local
2475 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2476 wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; in qcom_nand_attach_chip()
2477 cwperpage = mtd->writesize / NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2480 * Each CW has 4 available OOB bytes which will be protected with ECC in qcom_nand_attach_chip()
2481 * so remaining bytes can be used for ECC. in qcom_nand_attach_chip()
2484 mtd->oobsize - (cwperpage * 4)); in qcom_nand_attach_chip()
2486 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2490 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
2491 /* 8 bit ECC defaults to BCH ECC on all platforms */ in qcom_nand_attach_chip()
2492 host->bch_enabled = true; in qcom_nand_attach_chip()
2496 host->ecc_bytes_hw = 14; in qcom_nand_attach_chip()
2497 host->spare_bytes = 0; in qcom_nand_attach_chip()
2498 host->bbm_size = 2; in qcom_nand_attach_chip()
2500 host->ecc_bytes_hw = 13; in qcom_nand_attach_chip()
2501 host->spare_bytes = 2; in qcom_nand_attach_chip()
2502 host->bbm_size = 1; in qcom_nand_attach_chip()
2506 * if the controller supports BCH for 4 bit ECC, the controller in qcom_nand_attach_chip()
2507 * uses lesser bytes for ECC. If RS is used, the ECC bytes is in qcom_nand_attach_chip()
2510 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2512 host->bch_enabled = true; in qcom_nand_attach_chip()
2516 host->ecc_bytes_hw = 8; in qcom_nand_attach_chip()
2517 host->spare_bytes = 2; in qcom_nand_attach_chip()
2518 host->bbm_size = 2; in qcom_nand_attach_chip()
2520 host->ecc_bytes_hw = 7; in qcom_nand_attach_chip()
2521 host->spare_bytes = 4; in qcom_nand_attach_chip()
2522 host->bbm_size = 1; in qcom_nand_attach_chip()
2526 host->ecc_bytes_hw = 10; in qcom_nand_attach_chip()
2529 host->spare_bytes = 0; in qcom_nand_attach_chip()
2530 host->bbm_size = 2; in qcom_nand_attach_chip()
2532 host->spare_bytes = 1; in qcom_nand_attach_chip()
2533 host->bbm_size = 1; in qcom_nand_attach_chip()
2539 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
2541 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit in qcom_nand_attach_chip()
2542 * ECC and 12 bytes for 4 bit ECC in qcom_nand_attach_chip()
2544 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
2546 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
2547 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
2548 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
2549 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
2550 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
2551 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
2553 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
2557 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2562 * spare data with ECC too. We protect spare data by default, so we set in qcom_nand_attach_chip()
2565 host->cw_data = 516; in qcom_nand_attach_chip()
2568 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes in qcom_nand_attach_chip()
2569 * for 8 bit ECC in qcom_nand_attach_chip()
2571 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
2572 bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1; in qcom_nand_attach_chip()
2574 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
2575 | host->cw_data << UD_SIZE_BYTES in qcom_nand_attach_chip()
2578 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS in qcom_nand_attach_chip()
2581 | host->spare_bytes << SPARE_SIZE_BYTES; in qcom_nand_attach_chip()
2583 host->cfg1 = 7 << NAND_RECOVERY_CYCLES in qcom_nand_attach_chip()
2589 | host->bch_enabled << ENABLE_BCH_ECC; in qcom_nand_attach_chip()
2591 host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
2592 | host->cw_size << UD_SIZE_BYTES in qcom_nand_attach_chip()
2596 host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES in qcom_nand_attach_chip()
2604 host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE in qcom_nand_attach_chip()
2606 | host->cw_data << ECC_NUM_DATA_BYTES in qcom_nand_attach_chip()
2609 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH; in qcom_nand_attach_chip()
2611 host->ecc_buf_cfg = 0x203 << NUM_STEPS; in qcom_nand_attach_chip()
2613 host->clrflashstatus = FS_READY_BSY_N; in qcom_nand_attach_chip()
2614 host->clrreadstatus = 0xc0; in qcom_nand_attach_chip()
2615 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2617 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2620 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2622 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
2623 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
2635 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2636 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2637 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2639 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2642 if (nandc->tx_chan) in qcom_nandc_unalloc()
2643 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2645 if (nandc->rx_chan) in qcom_nandc_unalloc()
2646 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2648 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2649 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2651 if (nandc->chan) in qcom_nandc_unalloc()
2652 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2660 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2662 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2668 * data like ID and status, and preforming read-copy-write operations in qcom_nandc_alloc()
2670 * size of a codeword for our nand controller in qcom_nandc_alloc()
2672 nandc->buf_size = 532; in qcom_nandc_alloc()
2674 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2676 if (!nandc->data_buffer) in qcom_nandc_alloc()
2677 return -ENOMEM; in qcom_nandc_alloc()
2679 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2681 if (!nandc->regs) in qcom_nandc_alloc()
2682 return -ENOMEM; in qcom_nandc_alloc()
2684 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2685 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2687 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2688 return -ENOMEM; in qcom_nandc_alloc()
2690 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2691 nandc->reg_read_dma = in qcom_nandc_alloc()
2692 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2694 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2696 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2697 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2698 return -EIO; in qcom_nandc_alloc()
2701 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
2702 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
2703 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
2704 nandc->tx_chan = NULL; in qcom_nandc_alloc()
2705 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2710 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
2711 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
2712 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
2713 nandc->rx_chan = NULL; in qcom_nandc_alloc()
2714 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2719 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
2720 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
2721 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
2722 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
2723 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2734 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2735 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2736 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2737 dev_err(nandc->dev, in qcom_nandc_alloc()
2739 ret = -ENOMEM; in qcom_nandc_alloc()
2743 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2744 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
2745 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
2746 nandc->chan = NULL; in qcom_nandc_alloc()
2747 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2753 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2754 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2756 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2757 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2765 /* one time setup of a few nand controller registers */
2771 if (!nandc->props->is_qpic) in qcom_nandc_setup()
2777 if (nandc->props->is_bam) { in qcom_nandc_setup()
2794 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2795 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2804 struct nand_chip *chip = &host->chip; in qcom_nand_host_init_and_register()
2806 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2809 ret = of_property_read_u32(dn, "reg", &host->cs); in qcom_nand_host_init_and_register()
2811 dev_err(dev, "can't get chip-select\n"); in qcom_nand_host_init_and_register()
2812 return -ENXIO; in qcom_nand_host_init_and_register()
2816 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs); in qcom_nand_host_init_and_register()
2817 if (!mtd->name) in qcom_nand_host_init_and_register()
2818 return -ENOMEM; in qcom_nand_host_init_and_register()
2820 mtd->owner = THIS_MODULE; in qcom_nand_host_init_and_register()
2821 mtd->dev.parent = dev; in qcom_nand_host_init_and_register()
2823 chip->legacy.cmdfunc = qcom_nandc_command; in qcom_nand_host_init_and_register()
2824 chip->legacy.select_chip = qcom_nandc_select_chip; in qcom_nand_host_init_and_register()
2825 chip->legacy.read_byte = qcom_nandc_read_byte; in qcom_nand_host_init_and_register()
2826 chip->legacy.read_buf = qcom_nandc_read_buf; in qcom_nand_host_init_and_register()
2827 chip->legacy.write_buf = qcom_nandc_write_buf; in qcom_nand_host_init_and_register()
2828 chip->legacy.set_features = nand_get_set_features_notsupp; in qcom_nand_host_init_and_register()
2829 chip->legacy.get_features = nand_get_set_features_notsupp; in qcom_nand_host_init_and_register()
2833 * of a page with ECC disabled. currently, the nand_base and nand_bbt in qcom_nand_host_init_and_register()
2834 * helpers don't allow us to read BB from a nand chip with ECC in qcom_nand_host_init_and_register()
2839 chip->legacy.block_bad = qcom_nandc_block_bad; in qcom_nand_host_init_and_register()
2840 chip->legacy.block_markbad = qcom_nandc_block_markbad; in qcom_nand_host_init_and_register()
2842 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2843 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | in qcom_nand_host_init_and_register()
2847 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_nand_host_init_and_register()
2853 if (nandc->props->is_bam) { in qcom_nand_host_init_and_register()
2855 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2856 if (!nandc->bam_txn) { in qcom_nand_host_init_and_register()
2857 dev_err(nandc->dev, in qcom_nand_host_init_and_register()
2859 return -ENOMEM; in qcom_nand_host_init_and_register()
2872 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2873 struct device_node *dn = dev->of_node, *child; in qcom_probe_nand_devices()
2881 return -ENOMEM; in qcom_probe_nand_devices()
2890 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2893 if (list_empty(&nandc->host_list)) in qcom_probe_nand_devices()
2894 return -ENODEV; in qcom_probe_nand_devices()
2903 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2906 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
2907 ret = of_property_read_u32(np, "qcom,cmd-crci", in qcom_nandc_parse_dt()
2908 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2910 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2914 ret = of_property_read_u32(np, "qcom,data-crci", in qcom_nandc_parse_dt()
2915 &nandc->data_crci); in qcom_nandc_parse_dt()
2917 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2929 struct device *dev = &pdev->dev; in qcom_nandc_probe()
2933 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
2935 return -ENOMEM; in qcom_nandc_probe()
2938 nandc->dev = dev; in qcom_nandc_probe()
2942 dev_err(&pdev->dev, "failed to get device data\n"); in qcom_nandc_probe()
2943 return -ENODEV; in qcom_nandc_probe()
2946 nandc->props = dev_data; in qcom_nandc_probe()
2948 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2949 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2950 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2952 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2953 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2954 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2961 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
2962 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2963 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2965 nandc->base_phys = res->start; in qcom_nandc_probe()
2966 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2969 if (!nandc->base_dma) in qcom_nandc_probe()
2970 return -ENXIO; in qcom_nandc_probe()
2976 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2980 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2995 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2997 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
3001 dma_unmap_resource(dev, res->start, resource_size(res), in qcom_nandc_probe()
3015 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3016 chip = &host->chip; in qcom_nandc_remove()
3024 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3025 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3027 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()
3059 .compatible = "qcom,ipq806x-nand",
3063 .compatible = "qcom,ipq4019-nand",
3067 .compatible = "qcom,ipq8074-nand",
3076 .name = "qcom-nandc",
3085 MODULE_DESCRIPTION("Qualcomm NAND Controller driver");