Lines Matching +full:nand +full:- +full:no +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
29 * on NAND flash memory. Driver uses CDMA mode for
88 /* Command Engine threads state. */
91 /* Command Engine interrupt thread error status. */
93 /* Command Engine interrupt thread error enable. */
95 /* Command Engine interrupt thread complete status. */
115 /* Size of not-last data sector. */
118 /* ECC engine configuration register 0. */
124 /* Enable controller ECC check bits generation and correction. */
127 /* ECC engine configuration register 1. */
159 /* Support for NV-DDR2/3 work mode. */
161 /* Support for NV-DDR work mode. */
172 /* BCH Engine identification register 0 - correction strengths. */
179 /* BCH Engine identification register 1 - correction strengths. */
186 /* BCH Engine identification register 2 - sector sizes. */
191 /* BCH Engine identification register 3. */
200 /* 16 bit device connected to the NAND Flash interface. */
292 /* Generic command address sequence - address fields. */
294 /* Generic command address sequence - address size. */
304 /* ECC enabled flag of generic command data sequence - ECC enabled. */
306 /* Generic command data sequence - sector size. */
308 /* Generic command data sequence - sector count. */
310 /* Generic command data sequence - last sector size. */
332 * Command DMA descriptor flags - the next descriptor
342 /* Command descriptor status - operation fail. */
344 /* Command descriptor status - page erased. */
346 /* Command descriptor status - timeout occurred. */
349 * Maximum amount of correction applied to one ECC sector.
353 /* Command descriptor status - uncorrectable ECC error. */
355 /* Command descriptor status - descriptor error. */
358 /* Status of operation - OK. */
360 /* Status of operation - FAIL. */
362 /* Status of operation - uncorrectable ECC error. */
364 /* Status of operation - page erased. */
366 /* Status of operation - correctable ECC error. */
368 /* Status of operation - unsuspected state. */
370 /* Status of operation - operation is not completed yet. */
392 /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
433 /* Cadence NAND flash controller capabilities get from driver data. */
435 /* Skew value of the output signals of the NAND Flash interface. */
437 /* It informs if slave DMA interface is connected to DMA engine. */
441 /* Cadence NAND flash controller capabilities read from registers. */
513 * part of oob area of NAND flash memory page.
518 /* Sector size. There are few sectors per mtd->writesize */
526 /* ECC strength index. */
553 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_dma_buf_ok()
567 ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset, in cadence_nand_wait_for_value()
572 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_value()
588 return -ETIMEDOUT; in cadence_nand_set_ecc_enable()
590 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_enable()
597 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_enable()
607 if (cdns_ctrl->curr_corr_str_idx == corr_str_idx) in cadence_nand_set_ecc_strength()
610 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_strength()
613 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_strength()
615 cdns_ctrl->curr_corr_str_idx = corr_str_idx; in cadence_nand_set_ecc_strength()
621 int i, corr_str_idx = -1; in cadence_nand_get_ecc_strength_idx()
624 if (cdns_ctrl->ecc_strengths[i] == strength) { in cadence_nand_get_ecc_strength_idx()
641 return -ETIMEDOUT; in cadence_nand_set_skip_marker_val()
643 reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_marker_val()
648 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_marker_val()
663 return -ETIMEDOUT; in cadence_nand_set_skip_bytes_conf()
670 reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_bytes_conf()
677 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_bytes_conf()
678 writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET); in cadence_nand_set_skip_bytes_conf()
690 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_erase_detection()
697 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_erase_detection()
698 writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1); in cadence_nand_set_erase_detection()
709 return -ETIMEDOUT; in cadence_nand_set_access_width16()
711 reg = readl_relaxed(cdns_ctrl->reg + COMMON_SET); in cadence_nand_set_access_width16()
717 writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET); in cadence_nand_set_access_width16()
726 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
727 writel_relaxed(irq_status->trd_status, in cadence_nand_clear_interrupt()
728 cdns_ctrl->reg + TRD_COMP_INT_STATUS); in cadence_nand_clear_interrupt()
729 writel_relaxed(irq_status->trd_error, in cadence_nand_clear_interrupt()
730 cdns_ctrl->reg + TRD_ERR_INT_STATUS); in cadence_nand_clear_interrupt()
737 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
738 irq_status->trd_status = readl_relaxed(cdns_ctrl->reg in cadence_nand_read_int_status()
740 irq_status->trd_error = readl_relaxed(cdns_ctrl->reg in cadence_nand_read_int_status()
749 return irq_status->status || irq_status->trd_status || in irq_detected()
750 irq_status->trd_error; in irq_detected()
757 spin_lock_irqsave(&cdns_ctrl->irq_lock, flags); in cadence_nand_reset_irq()
758 memset(&cdns_ctrl->irq_status, 0, sizeof(cdns_ctrl->irq_status)); in cadence_nand_reset_irq()
759 memset(&cdns_ctrl->irq_mask, 0, sizeof(cdns_ctrl->irq_mask)); in cadence_nand_reset_irq()
760 spin_unlock_irqrestore(&cdns_ctrl->irq_lock, flags); in cadence_nand_reset_irq()
773 spin_lock(&cdns_ctrl->irq_lock); in cadence_nand_isr()
780 cdns_ctrl->irq_status.status |= irq_status.status; in cadence_nand_isr()
781 cdns_ctrl->irq_status.trd_status |= irq_status.trd_status; in cadence_nand_isr()
782 cdns_ctrl->irq_status.trd_error |= irq_status.trd_error; in cadence_nand_isr()
784 complete(&cdns_ctrl->complete); in cadence_nand_isr()
788 spin_unlock(&cdns_ctrl->irq_lock); in cadence_nand_isr()
796 writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status, in cadence_nand_set_irq_mask()
797 cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_set_irq_mask()
799 writel_relaxed(irq_mask->trd_error, in cadence_nand_set_irq_mask()
800 cdns_ctrl->reg + TRD_ERR_INT_STATUS_EN); in cadence_nand_set_irq_mask()
811 time_left = wait_for_completion_timeout(&cdns_ctrl->complete, in cadence_nand_wait_for_irq()
814 *irq_status = cdns_ctrl->irq_status; in cadence_nand_wait_for_irq()
817 dev_err(cdns_ctrl->dev, "timeout occurred:\n"); in cadence_nand_wait_for_irq()
818 dev_err(cdns_ctrl->dev, "\tstatus = 0x%x, mask = 0x%x\n", in cadence_nand_wait_for_irq()
819 irq_status->status, irq_mask->status); in cadence_nand_wait_for_irq()
820 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_irq()
822 irq_status->trd_status, irq_mask->trd_status); in cadence_nand_wait_for_irq()
823 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_irq()
825 irq_status->trd_error, irq_mask->trd_error); in cadence_nand_wait_for_irq()
829 /* Execute generic command on NAND controller. */
843 return -ETIMEDOUT; in cadence_nand_generic_cmd_send()
847 writel_relaxed(mini_ctrl_cmd_l, cdns_ctrl->reg + CMD_REG2); in cadence_nand_generic_cmd_send()
848 writel_relaxed(mini_ctrl_cmd_h, cdns_ctrl->reg + CMD_REG3); in cadence_nand_generic_cmd_send()
856 writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0); in cadence_nand_generic_cmd_send()
877 dev_err(cdns_ctrl->dev, "Timeout while waiting for SDMA\n"); in cadence_nand_wait_on_sdma()
878 return -ETIMEDOUT; in cadence_nand_wait_on_sdma()
882 *out_sdma_size = readl_relaxed(cdns_ctrl->reg + SDMA_SIZE); in cadence_nand_wait_on_sdma()
883 *out_sdma_trd = readl_relaxed(cdns_ctrl->reg + SDMA_TRD_NUM); in cadence_nand_wait_on_sdma()
887 dev_err(cdns_ctrl->dev, "SDMA error - irq_status %x\n", in cadence_nand_wait_on_sdma()
889 return -EIO; in cadence_nand_wait_on_sdma()
899 reg = readl_relaxed(cdns_ctrl->reg + CTRL_FEATURES); in cadence_nand_get_caps()
901 cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); in cadence_nand_get_caps()
904 cdns_ctrl->caps2.data_dma_width = 8; in cadence_nand_get_caps()
906 cdns_ctrl->caps2.data_dma_width = 4; in cadence_nand_get_caps()
909 cdns_ctrl->caps2.data_control_supp = true; in cadence_nand_get_caps()
913 cdns_ctrl->caps2.is_phy_type_dll = true; in cadence_nand_get_caps()
922 struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc; in cadence_nand_cdma_desc_prepare()
927 cdma_desc->flash_pointer = flash_ptr; in cadence_nand_cdma_desc_prepare()
928 if (cdns_ctrl->ctrl_rev >= 13) in cadence_nand_cdma_desc_prepare()
929 cdma_desc->bank = nf_mem; in cadence_nand_cdma_desc_prepare()
931 cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT); in cadence_nand_cdma_desc_prepare()
933 cdma_desc->command_flags |= CDMA_CF_DMA_MASTER; in cadence_nand_cdma_desc_prepare()
934 cdma_desc->command_flags |= CDMA_CF_INT; in cadence_nand_cdma_desc_prepare()
936 cdma_desc->memory_pointer = mem_ptr; in cadence_nand_cdma_desc_prepare()
937 cdma_desc->status = 0; in cadence_nand_cdma_desc_prepare()
938 cdma_desc->sync_flag_pointer = 0; in cadence_nand_cdma_desc_prepare()
939 cdma_desc->sync_arguments = 0; in cadence_nand_cdma_desc_prepare()
941 cdma_desc->command_type = ctype; in cadence_nand_cdma_desc_prepare()
942 cdma_desc->ctrl_data_ptr = ctrl_data_ptr; in cadence_nand_cdma_desc_prepare()
955 dev_err(cdns_ctrl->dev, ":CDMA desc error flag detected.\n"); in cadence_nand_check_desc_error()
967 struct cadence_nand_cdma_desc *desc_ptr = cdns_ctrl->cdma_desc; in cadence_nand_cdma_finish()
970 if (desc_ptr->status & CDMA_CS_FAIL) { in cadence_nand_cdma_finish()
972 desc_ptr->status); in cadence_nand_cdma_finish()
973 dev_err(cdns_ctrl->dev, ":CDMA error %x\n", desc_ptr->status); in cadence_nand_cdma_finish()
974 } else if (desc_ptr->status & CDMA_CS_COMP) { in cadence_nand_cdma_finish()
975 /* Descriptor finished with no errors. */ in cadence_nand_cdma_finish()
976 if (desc_ptr->command_flags & CDMA_CF_CONT) { in cadence_nand_cdma_finish()
977 dev_info(cdns_ctrl->dev, "DMA unsupported flag is set"); in cadence_nand_cdma_finish()
1002 reinit_completion(&cdns_ctrl->complete); in cadence_nand_cdma_send()
1004 writel_relaxed((u32)cdns_ctrl->dma_cdma_desc, in cadence_nand_cdma_send()
1005 cdns_ctrl->reg + CMD_REG2); in cadence_nand_cdma_send()
1006 writel_relaxed(0, cdns_ctrl->reg + CMD_REG3); in cadence_nand_cdma_send()
1013 writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0); in cadence_nand_cdma_send()
1040 dev_err(cdns_ctrl->dev, "CDMA command timeout\n"); in cadence_nand_cdma_send_and_wait()
1041 return -ETIMEDOUT; in cadence_nand_cdma_send_and_wait()
1044 dev_err(cdns_ctrl->dev, "CDMA command failed\n"); in cadence_nand_cdma_send_and_wait()
1045 return -EIO; in cadence_nand_cdma_send_and_wait()
1052 * ECC size depends on configured ECC strength and on maximum supported
1053 * ECC step size.
1079 struct nand_ecc_caps *ecc_caps = &cdns_ctrl->ecc_caps; in cadence_nand_read_bch_caps()
1083 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3); in cadence_nand_read_bch_caps()
1084 cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg); in cadence_nand_read_bch_caps()
1085 if (cdns_ctrl->bch_metadata_size < 4) { in cadence_nand_read_bch_caps()
1086 dev_err(cdns_ctrl->dev, in cadence_nand_read_bch_caps()
1088 return -EIO; in cadence_nand_read_bch_caps()
1091 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0); in cadence_nand_read_bch_caps()
1092 cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg); in cadence_nand_read_bch_caps()
1093 cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg); in cadence_nand_read_bch_caps()
1094 cdns_ctrl->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg); in cadence_nand_read_bch_caps()
1095 cdns_ctrl->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg); in cadence_nand_read_bch_caps()
1097 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_1); in cadence_nand_read_bch_caps()
1098 cdns_ctrl->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg); in cadence_nand_read_bch_caps()
1099 cdns_ctrl->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg); in cadence_nand_read_bch_caps()
1100 cdns_ctrl->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg); in cadence_nand_read_bch_caps()
1101 cdns_ctrl->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg); in cadence_nand_read_bch_caps()
1103 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_2); in cadence_nand_read_bch_caps()
1104 cdns_ctrl->ecc_stepinfos[0].stepsize = in cadence_nand_read_bch_caps()
1107 cdns_ctrl->ecc_stepinfos[1].stepsize = in cadence_nand_read_bch_caps()
1112 if (cdns_ctrl->ecc_strengths[i] != 0) in cadence_nand_read_bch_caps()
1116 ecc_caps->nstepinfos = 0; in cadence_nand_read_bch_caps()
1118 /* ECC strengths are common for all step infos. */ in cadence_nand_read_bch_caps()
1119 cdns_ctrl->ecc_stepinfos[i].nstrengths = nstrengths; in cadence_nand_read_bch_caps()
1120 cdns_ctrl->ecc_stepinfos[i].strengths = in cadence_nand_read_bch_caps()
1121 cdns_ctrl->ecc_strengths; in cadence_nand_read_bch_caps()
1123 if (cdns_ctrl->ecc_stepinfos[i].stepsize != 0) in cadence_nand_read_bch_caps()
1124 ecc_caps->nstepinfos++; in cadence_nand_read_bch_caps()
1126 if (cdns_ctrl->ecc_stepinfos[i].stepsize > max_step_size) in cadence_nand_read_bch_caps()
1127 max_step_size = cdns_ctrl->ecc_stepinfos[i].stepsize; in cadence_nand_read_bch_caps()
1129 ecc_caps->stepinfos = &cdns_ctrl->ecc_stepinfos[0]; in cadence_nand_read_bch_caps()
1133 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256; in cadence_nand_read_bch_caps()
1136 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512; in cadence_nand_read_bch_caps()
1139 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024; in cadence_nand_read_bch_caps()
1142 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048; in cadence_nand_read_bch_caps()
1145 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096; in cadence_nand_read_bch_caps()
1148 dev_err(cdns_ctrl->dev, in cadence_nand_read_bch_caps()
1149 "Unsupported sector size(ecc step size) %d\n", in cadence_nand_read_bch_caps()
1151 return -EIO; in cadence_nand_read_bch_caps()
1169 reg = readl_relaxed(cdns_ctrl->reg + CTRL_VERSION); in cadence_nand_hw_init()
1170 cdns_ctrl->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg); in cadence_nand_hw_init()
1172 dev_info(cdns_ctrl->dev, in cadence_nand_hw_init()
1173 "%s: cadence nand controller version reg %x\n", in cadence_nand_hw_init()
1177 writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG); in cadence_nand_hw_init()
1178 writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG); in cadence_nand_hw_init()
1181 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
1185 return -EIO; in cadence_nand_hw_init()
1207 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_prepare_data_size()
1211 u32 last_sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1215 if (cdns_ctrl->curr_trans_type == transfer_type) in cadence_nand_prepare_data_size()
1220 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1221 sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1222 data_ctrl_size = cdns_chip->avail_oob_size; in cadence_nand_prepare_data_size()
1225 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1226 last_sec_size = cdns_chip->sector_size in cadence_nand_prepare_data_size()
1227 + cdns_chip->avail_oob_size; in cadence_nand_prepare_data_size()
1228 sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1231 last_sec_size = mtd->writesize + mtd->oobsize; in cadence_nand_prepare_data_size()
1234 offset = mtd->writesize + cdns_chip->bbm_offs; in cadence_nand_prepare_data_size()
1242 writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_0); in cadence_nand_prepare_data_size()
1247 writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_1); in cadence_nand_prepare_data_size()
1249 if (cdns_ctrl->caps2.data_control_supp) { in cadence_nand_prepare_data_size()
1250 reg = readl_relaxed(cdns_ctrl->reg + CONTROL_DATA_CTRL); in cadence_nand_prepare_data_size()
1253 writel_relaxed(reg, cdns_ctrl->reg + CONTROL_DATA_CTRL); in cadence_nand_prepare_data_size()
1256 cdns_ctrl->curr_trans_type = transfer_type; in cadence_nand_prepare_data_size()
1277 dma_buf = dma_map_single(cdns_ctrl->dev, buf, buf_size, dir); in cadence_nand_cdma_transfer()
1278 if (dma_mapping_error(cdns_ctrl->dev, dma_buf)) { in cadence_nand_cdma_transfer()
1279 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_cdma_transfer()
1280 return -EIO; in cadence_nand_cdma_transfer()
1284 dma_ctrl_dat = dma_map_single(cdns_ctrl->dev, ctrl_dat, in cadence_nand_cdma_transfer()
1286 if (dma_mapping_error(cdns_ctrl->dev, dma_ctrl_dat)) { in cadence_nand_cdma_transfer()
1287 dma_unmap_single(cdns_ctrl->dev, dma_buf, in cadence_nand_cdma_transfer()
1289 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_cdma_transfer()
1290 return -EIO; in cadence_nand_cdma_transfer()
1299 dma_unmap_single(cdns_ctrl->dev, dma_buf, in cadence_nand_cdma_transfer()
1303 dma_unmap_single(cdns_ctrl->dev, dma_ctrl_dat, in cadence_nand_cdma_transfer()
1314 writel_relaxed(t->async_toggle_timings, in cadence_nand_set_timings()
1315 cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS); in cadence_nand_set_timings()
1316 writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0); in cadence_nand_set_timings()
1317 writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1); in cadence_nand_set_timings()
1318 writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2); in cadence_nand_set_timings()
1320 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_set_timings()
1321 writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL); in cadence_nand_set_timings()
1323 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
1325 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_set_timings()
1326 writel_relaxed(0, cdns_ctrl->reg + PHY_TSEL); in cadence_nand_set_timings()
1327 writel_relaxed(2, cdns_ctrl->reg + PHY_DQ_TIMING); in cadence_nand_set_timings()
1328 writel_relaxed(t->phy_dqs_timing, in cadence_nand_set_timings()
1329 cdns_ctrl->reg + PHY_DQS_TIMING); in cadence_nand_set_timings()
1330 writel_relaxed(t->phy_gate_lpbk_ctrl, in cadence_nand_set_timings()
1331 cdns_ctrl->reg + PHY_GATE_LPBK_CTRL); in cadence_nand_set_timings()
1333 cdns_ctrl->reg + PHY_DLL_MASTER_CTRL); in cadence_nand_set_timings()
1334 writel_relaxed(0, cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL); in cadence_nand_set_timings()
1340 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_select_target()
1343 if (chip == cdns_ctrl->selected_chip) in cadence_nand_select_target()
1349 return -ETIMEDOUT; in cadence_nand_select_target()
1351 cadence_nand_set_timings(cdns_ctrl, &cdns_chip->timings); in cadence_nand_select_target()
1354 cdns_chip->corr_str_idx); in cadence_nand_select_target()
1357 chip->ecc.strength); in cadence_nand_select_target()
1359 cdns_ctrl->curr_trans_type = -1; in cadence_nand_select_target()
1360 cdns_ctrl->selected_chip = chip; in cadence_nand_select_target()
1367 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_erase()
1370 u8 thread_nr = cdns_chip->cs[chip->cur_cs]; in cadence_nand_erase()
1373 cdns_chip->cs[chip->cur_cs], in cadence_nand_erase()
1378 dev_err(cdns_ctrl->dev, "erase operation failed\n"); in cadence_nand_erase()
1379 return -EIO; in cadence_nand_erase()
1392 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_bbm()
1405 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_bbm()
1406 page, cdns_ctrl->buf, NULL, in cadence_nand_read_bbm()
1407 mtd->oobsize, in cadence_nand_read_bbm()
1410 dev_err(cdns_ctrl->dev, "read BBM failed\n"); in cadence_nand_read_bbm()
1411 return -EIO; in cadence_nand_read_bbm()
1414 memcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len); in cadence_nand_read_bbm()
1423 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_page()
1433 cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len, in cadence_nand_write_page()
1434 mtd->writesize in cadence_nand_write_page()
1435 + cdns_chip->bbm_offs, in cadence_nand_write_page()
1439 marker_val = *(u16 *)(chip->oob_poi in cadence_nand_write_page()
1440 + cdns_chip->bbm_offs); in cadence_nand_write_page()
1443 memset(cdns_ctrl->buf + mtd->writesize, 0xFF, in cadence_nand_write_page()
1444 cdns_chip->avail_oob_size); in cadence_nand_write_page()
1451 if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) && in cadence_nand_write_page()
1452 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_write_page()
1456 oob = chip->oob_poi; in cadence_nand_write_page()
1458 oob = cdns_ctrl->buf + mtd->writesize; in cadence_nand_write_page()
1461 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page()
1463 mtd->writesize, in cadence_nand_write_page()
1464 cdns_chip->avail_oob_size, in cadence_nand_write_page()
1467 dev_err(cdns_ctrl->dev, "write page failed\n"); in cadence_nand_write_page()
1468 return -EIO; in cadence_nand_write_page()
1476 memcpy(cdns_ctrl->buf + mtd->writesize, chip->oob_poi, in cadence_nand_write_page()
1477 cdns_chip->avail_oob_size); in cadence_nand_write_page()
1480 memcpy(cdns_ctrl->buf, buf, mtd->writesize); in cadence_nand_write_page()
1485 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page()
1486 page, cdns_ctrl->buf, NULL, in cadence_nand_write_page()
1487 mtd->writesize in cadence_nand_write_page()
1488 + cdns_chip->avail_oob_size, in cadence_nand_write_page()
1494 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_oob()
1497 memset(cdns_ctrl->buf, 0xFF, mtd->writesize); in cadence_nand_write_oob()
1499 return cadence_nand_write_page(chip, cdns_ctrl->buf, 1, page); in cadence_nand_write_oob()
1506 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_page_raw()
1509 int writesize = mtd->writesize; in cadence_nand_write_page_raw()
1510 int oobsize = mtd->oobsize; in cadence_nand_write_page_raw()
1511 int ecc_steps = chip->ecc.steps; in cadence_nand_write_page_raw()
1512 int ecc_size = chip->ecc.size; in cadence_nand_write_page_raw()
1513 int ecc_bytes = chip->ecc.bytes; in cadence_nand_write_page_raw()
1514 void *tmp_buf = cdns_ctrl->buf; in cadence_nand_write_page_raw()
1515 int oob_skip = cdns_chip->bbm_len; in cadence_nand_write_page_raw()
1533 /* Arrange the buffer for syndrome payload/ecc layout. */ in cadence_nand_write_page_raw()
1542 len = writesize - pos; in cadence_nand_write_page_raw()
1547 len = ecc_size - len; in cadence_nand_write_page_raw()
1556 const u8 *oob = chip->oob_poi; in cadence_nand_write_page_raw()
1557 u32 oob_data_offset = (cdns_chip->sector_count - 1) * in cadence_nand_write_page_raw()
1558 (cdns_chip->sector_size + chip->ecc.bytes) in cadence_nand_write_page_raw()
1559 + cdns_chip->sector_size + oob_skip; in cadence_nand_write_page_raw()
1566 cdns_chip->avail_oob_size); in cadence_nand_write_page_raw()
1567 oob += cdns_chip->avail_oob_size; in cadence_nand_write_page_raw()
1569 /* OOB ECC. */ in cadence_nand_write_page_raw()
1572 if (i == (ecc_steps - 1)) in cadence_nand_write_page_raw()
1573 pos += cdns_chip->avail_oob_size; in cadence_nand_write_page_raw()
1580 len = writesize - pos; in cadence_nand_write_page_raw()
1585 len = ecc_bytes - len; in cadence_nand_write_page_raw()
1596 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page_raw()
1597 page, cdns_ctrl->buf, NULL, in cadence_nand_write_page_raw()
1598 mtd->writesize + in cadence_nand_write_page_raw()
1599 mtd->oobsize, in cadence_nand_write_page_raw()
1612 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_page()
1622 cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len, in cadence_nand_read_page()
1623 mtd->writesize in cadence_nand_read_page()
1624 + cdns_chip->bbm_offs, 1); in cadence_nand_read_page()
1630 if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) && in cadence_nand_read_page()
1631 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_read_page()
1635 oob = chip->oob_poi; in cadence_nand_read_page()
1637 oob = cdns_ctrl->buf + mtd->writesize; in cadence_nand_read_page()
1641 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page()
1643 mtd->writesize, in cadence_nand_read_page()
1644 cdns_chip->avail_oob_size, in cadence_nand_read_page()
1650 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page()
1651 page, cdns_ctrl->buf, in cadence_nand_read_page()
1652 NULL, mtd->writesize in cadence_nand_read_page()
1653 + cdns_chip->avail_oob_size, in cadence_nand_read_page()
1656 memcpy(buf, cdns_ctrl->buf, mtd->writesize); in cadence_nand_read_page()
1658 memcpy(chip->oob_poi, in cadence_nand_read_page()
1659 cdns_ctrl->buf + mtd->writesize, in cadence_nand_read_page()
1660 mtd->oobsize); in cadence_nand_read_page()
1665 mtd->ecc_stats.failed++; in cadence_nand_read_page()
1670 cdns_ctrl->cdma_desc->status); in cadence_nand_read_page()
1671 mtd->ecc_stats.corrected += ecc_err_count; in cadence_nand_read_page()
1677 dev_err(cdns_ctrl->dev, "read page failed\n"); in cadence_nand_read_page()
1678 return -EIO; in cadence_nand_read_page()
1682 if (cadence_nand_read_bbm(chip, page, chip->oob_poi)) in cadence_nand_read_page()
1683 return -EIO; in cadence_nand_read_page()
1691 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_oob()
1693 return cadence_nand_read_page(chip, cdns_ctrl->buf, 1, page); in cadence_nand_read_oob()
1699 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_page_raw()
1702 int oob_skip = cdns_chip->bbm_len; in cadence_nand_read_page_raw()
1703 int writesize = mtd->writesize; in cadence_nand_read_page_raw()
1704 int ecc_steps = chip->ecc.steps; in cadence_nand_read_page_raw()
1705 int ecc_size = chip->ecc.size; in cadence_nand_read_page_raw()
1706 int ecc_bytes = chip->ecc.bytes; in cadence_nand_read_page_raw()
1707 void *tmp_buf = cdns_ctrl->buf; in cadence_nand_read_page_raw()
1719 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page_raw()
1720 page, cdns_ctrl->buf, NULL, in cadence_nand_read_page_raw()
1721 mtd->writesize in cadence_nand_read_page_raw()
1722 + mtd->oobsize, in cadence_nand_read_page_raw()
1730 dev_err(cdns_ctrl->dev, "read raw page failed\n"); in cadence_nand_read_page_raw()
1731 return -EIO; in cadence_nand_read_page_raw()
1734 /* Arrange the buffer for syndrome payload/ecc layout. */ in cadence_nand_read_page_raw()
1743 len = writesize - pos; in cadence_nand_read_page_raw()
1748 len = ecc_size - len; in cadence_nand_read_page_raw()
1757 u8 *oob = chip->oob_poi; in cadence_nand_read_page_raw()
1758 u32 oob_data_offset = (cdns_chip->sector_count - 1) * in cadence_nand_read_page_raw()
1759 (cdns_chip->sector_size + chip->ecc.bytes) in cadence_nand_read_page_raw()
1760 + cdns_chip->sector_size + oob_skip; in cadence_nand_read_page_raw()
1764 cdns_chip->avail_oob_size); in cadence_nand_read_page_raw()
1769 oob += cdns_chip->avail_oob_size; in cadence_nand_read_page_raw()
1771 /* OOB ECC */ in cadence_nand_read_page_raw()
1776 if (i == (ecc_steps - 1)) in cadence_nand_read_page_raw()
1777 pos += cdns_chip->avail_oob_size; in cadence_nand_read_page_raw()
1782 len = writesize - pos; in cadence_nand_read_page_raw()
1787 len = ecc_bytes - len; in cadence_nand_read_page_raw()
1823 chan = cdns_ctrl->dmac; in cadence_nand_slave_dma_transfer()
1824 dma_dev = chan->device; in cadence_nand_slave_dma_transfer()
1826 buf_dma = dma_map_single(dma_dev->dev, buf, len, dir); in cadence_nand_slave_dma_transfer()
1827 if (dma_mapping_error(dma_dev->dev, buf_dma)) { in cadence_nand_slave_dma_transfer()
1828 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_slave_dma_transfer()
1833 src_dma = cdns_ctrl->io.dma; in cadence_nand_slave_dma_transfer()
1837 dst_dma = cdns_ctrl->io.dma; in cadence_nand_slave_dma_transfer()
1840 tx = dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len, in cadence_nand_slave_dma_transfer()
1843 dev_err(cdns_ctrl->dev, "Failed to prepare DMA memcpy\n"); in cadence_nand_slave_dma_transfer()
1847 tx->callback = cadence_nand_slave_dma_transfer_finished; in cadence_nand_slave_dma_transfer()
1848 tx->callback_param = &finished; in cadence_nand_slave_dma_transfer()
1852 dev_err(cdns_ctrl->dev, "Failed to do DMA tx_submit\n"); in cadence_nand_slave_dma_transfer()
1856 dma_async_issue_pending(cdns_ctrl->dmac); in cadence_nand_slave_dma_transfer()
1859 dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir); in cadence_nand_slave_dma_transfer()
1864 dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir); in cadence_nand_slave_dma_transfer()
1867 dev_dbg(cdns_ctrl->dev, "Fall back to CPU I/O\n"); in cadence_nand_slave_dma_transfer()
1869 return -EIO; in cadence_nand_slave_dma_transfer()
1884 if (!cdns_ctrl->caps1->has_dma) { in cadence_nand_read_buf()
1888 ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_read_buf()
1891 ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, in cadence_nand_read_buf()
1892 sdma_size / 4 - len_in_words); in cadence_nand_read_buf()
1894 memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, in cadence_nand_read_buf()
1895 len - (len_in_words << 2)); in cadence_nand_read_buf()
1902 cdns_ctrl->io.dma, in cadence_nand_read_buf()
1907 dev_warn(cdns_ctrl->dev, in cadence_nand_read_buf()
1912 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, in cadence_nand_read_buf()
1913 cdns_ctrl->io.dma, in cadence_nand_read_buf()
1917 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); in cadence_nand_read_buf()
1921 memcpy(buf, cdns_ctrl->buf, len); in cadence_nand_read_buf()
1938 if (!cdns_ctrl->caps1->has_dma) { in cadence_nand_write_buf()
1941 iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_write_buf()
1944 memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), in cadence_nand_write_buf()
1945 len - (len_in_words << 2)); in cadence_nand_write_buf()
1946 /* write all expected by nand controller data */ in cadence_nand_write_buf()
1947 iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, in cadence_nand_write_buf()
1948 sdma_size / 4 - len_in_words); in cadence_nand_write_buf()
1956 cdns_ctrl->io.dma, in cadence_nand_write_buf()
1961 dev_warn(cdns_ctrl->dev, in cadence_nand_write_buf()
1966 memcpy(cdns_ctrl->buf, buf, len); in cadence_nand_write_buf()
1968 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, in cadence_nand_write_buf()
1969 cdns_ctrl->io.dma, in cadence_nand_write_buf()
1973 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); in cadence_nand_write_buf()
1981 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_force_byte_access()
1985 * Callers of this function do not verify if the NAND is using a 16-bit in cadence_nand_force_byte_access()
1986 * an 8-bit bus for normal operations, so we need to take care of that in cadence_nand_force_byte_access()
1987 * here by leaving the configuration unchanged if the NAND does not have in cadence_nand_force_byte_access()
1990 if (!(chip->options & NAND_BUSWIDTH_16)) in cadence_nand_force_byte_access()
2001 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_opcode()
2008 instr = &subop->instrs[op_id]; in cadence_nand_cmd_opcode()
2010 if (instr->delay_ns > 0) in cadence_nand_cmd_opcode()
2016 instr->ctx.cmd.opcode); in cadence_nand_cmd_opcode()
2019 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_opcode()
2022 dev_err(cdns_ctrl->dev, "send cmd %x failed\n", in cadence_nand_cmd_opcode()
2023 instr->ctx.cmd.opcode); in cadence_nand_cmd_opcode()
2031 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_address()
2042 instr = &subop->instrs[op_id]; in cadence_nand_cmd_address()
2044 if (instr->delay_ns > 0) in cadence_nand_cmd_address()
2052 addrs = &instr->ctx.addr.addrs[offset]; in cadence_nand_cmd_address()
2060 naddrs - 1); in cadence_nand_cmd_address()
2063 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_address()
2066 dev_err(cdns_ctrl->dev, "send address %llx failed\n", address); in cadence_nand_cmd_address()
2076 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) { in cadence_nand_cmd_erase()
2083 instr = &subop->instrs[1]; in cadence_nand_cmd_erase()
2086 addrs = &instr->ctx.addr.addrs[offset]; in cadence_nand_cmd_erase()
2098 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in cadence_nand_cmd_erase()
2101 .cs = chip->cur_cs, in cadence_nand_cmd_erase()
2102 .instrs = &subop->instrs[op_id], in cadence_nand_cmd_erase()
2104 ret = chip->controller->ops->exec_op(chip, &nand_op, false); in cadence_nand_cmd_erase()
2115 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_data()
2123 instr = &subop->instrs[op_id]; in cadence_nand_cmd_data()
2125 if (instr->delay_ns > 0) in cadence_nand_cmd_data()
2131 if (instr->type == NAND_OP_DATA_OUT_INSTR) in cadence_nand_cmd_data()
2139 if (instr->ctx.data.force_8bit) { in cadence_nand_cmd_data()
2142 dev_err(cdns_ctrl->dev, in cadence_nand_cmd_data()
2149 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_data()
2152 dev_err(cdns_ctrl->dev, "send generic data cmd failed\n"); in cadence_nand_cmd_data()
2156 if (instr->type == NAND_OP_DATA_IN_INSTR) { in cadence_nand_cmd_data()
2157 void *buf = instr->ctx.data.buf.in + offset; in cadence_nand_cmd_data()
2161 const void *buf = instr->ctx.data.buf.out + offset; in cadence_nand_cmd_data()
2167 dev_err(cdns_ctrl->dev, "data transfer failed for generic command\n"); in cadence_nand_cmd_data()
2171 if (instr->ctx.data.force_8bit) { in cadence_nand_cmd_data()
2174 dev_err(cdns_ctrl->dev, in cadence_nand_cmd_data()
2187 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_waitrdy()
2189 const struct nand_op_instr *instr = &subop->instrs[op_id]; in cadence_nand_cmd_waitrdy()
2190 u32 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000; in cadence_nand_cmd_waitrdy()
2194 BIT(cdns_chip->cs[chip->cur_cs]), in cadence_nand_cmd_waitrdy()
2245 return -ERANGE; in cadence_nand_ooblayout_free()
2247 oobregion->offset = cdns_chip->bbm_len; in cadence_nand_ooblayout_free()
2248 oobregion->length = cdns_chip->avail_oob_size in cadence_nand_ooblayout_free()
2249 - cdns_chip->bbm_len; in cadence_nand_ooblayout_free()
2261 return -ERANGE; in cadence_nand_ooblayout_ecc()
2263 oobregion->offset = cdns_chip->avail_oob_size; in cadence_nand_ooblayout_ecc()
2264 oobregion->length = chip->ecc.total; in cadence_nand_ooblayout_ecc()
2271 .ecc = cadence_nand_ooblayout_ecc,
2282 return timing / clock - 1; in calc_cycl()
2303 return (trp_cnt + 1) * clk_period + trhoh_min - trea_max; in calc_tdvw()
2311 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_setup_interface()
2313 struct cadence_nand_timings *t = &cdns_chip->timings; in cadence_nand_setup_interface()
2315 u32 board_delay = cdns_ctrl->board_delay; in cadence_nand_setup_interface()
2317 cdns_ctrl->nf_clk_rate); in cadence_nand_setup_interface()
2322 u32 if_skew = cdns_ctrl->caps1->if_skew; in cadence_nand_setup_interface()
2323 u32 board_delay_skew_min = board_delay - if_skew; in cadence_nand_setup_interface()
2338 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2345 tdvw_min = sdr->tREA_max + board_delay_skew_max; in cadence_nand_setup_interface()
2355 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_interface()
2356 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_interface()
2357 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_interface()
2360 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2361 sdr->tREA_max, ext_rd_mode); in cadence_nand_setup_interface()
2362 tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2374 * No valid sampling point so the RE pulse need in cadence_nand_setup_interface()
2381 * There is no valid window in cadence_nand_setup_interface()
2385 trp_cnt = (sdr->tREA_max + board_delay_skew_max in cadence_nand_setup_interface()
2395 trp_cnt = calc_cycl(sdr->tRP_min, clk_period); in cadence_nand_setup_interface()
2396 trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period); in cadence_nand_setup_interface()
2397 if (sdr->tREH_min >= trh) in cadence_nand_setup_interface()
2398 trh_cnt = calc_cycl(sdr->tREH_min, clk_period); in cadence_nand_setup_interface()
2402 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2403 sdr->tREA_max, ext_rd_mode); in cadence_nand_setup_interface()
2407 * - if not extend the tRP timings. in cadence_nand_setup_interface()
2411 sdr->tRHOH_min, in cadence_nand_setup_interface()
2418 (((tdvw_max / dqs_sampl_res - 1) in cadence_nand_setup_interface()
2431 * There is no valid window to be able to sample data. in cadence_nand_setup_interface()
2435 trp_cnt = (sdr->tREA_max + board_delay_skew_max in cadence_nand_setup_interface()
2441 sdr->tRHOH_min, in cadence_nand_setup_interface()
2444 if (sdr->tWC_min <= clk_period && in cadence_nand_setup_interface()
2445 (sdr->tWP_min + if_skew) <= (clk_period / 2) && in cadence_nand_setup_interface()
2446 (sdr->tWH_min + if_skew) <= (clk_period / 2)) { in cadence_nand_setup_interface()
2452 twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period); in cadence_nand_setup_interface()
2453 if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew)) in cadence_nand_setup_interface()
2454 twp_cnt = calc_cycl(sdr->tALS_min + if_skew, in cadence_nand_setup_interface()
2457 twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period); in cadence_nand_setup_interface()
2458 if (sdr->tWH_min >= twh) in cadence_nand_setup_interface()
2459 twh = sdr->tWH_min; in cadence_nand_setup_interface()
2468 t->async_toggle_timings = reg; in cadence_nand_setup_interface()
2469 dev_dbg(cdns_ctrl->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2471 tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period); in cadence_nand_setup_interface()
2472 tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
2473 twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period); in cadence_nand_setup_interface()
2474 trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period); in cadence_nand_setup_interface()
2488 t->timings0 = reg; in cadence_nand_setup_interface()
2489 dev_dbg(cdns_ctrl->dev, "TIMINGS0_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2492 trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period); in cadence_nand_setup_interface()
2494 twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period); in cadence_nand_setup_interface()
2509 t->timings1 = reg; in cadence_nand_setup_interface()
2510 dev_dbg(cdns_ctrl->dev, "TIMINGS1_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2512 tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period); in cadence_nand_setup_interface()
2516 tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period); in cadence_nand_setup_interface()
2517 tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
2522 t->timings2 = reg; in cadence_nand_setup_interface()
2523 dev_dbg(cdns_ctrl->dev, "TIMINGS2_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2525 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2534 t->dll_phy_ctrl = reg; in cadence_nand_setup_interface()
2535 dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2542 sampling_point = (tdvw_max / dqs_sampl_res - 1); in cadence_nand_setup_interface()
2558 / phony_dqs_mod - 1; in cadence_nand_setup_interface()
2560 if (!cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2561 phony_dqs_timing--; in cadence_nand_setup_interface()
2564 phony_dqs_timing--; in cadence_nand_setup_interface()
2568 dev_warn(cdns_ctrl->dev, in cadence_nand_setup_interface()
2573 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2575 t->phy_ctrl = reg; in cadence_nand_setup_interface()
2576 dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2578 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2579 dev_dbg(cdns_ctrl->dev, "PHY_TSEL_REG_SDR\t%x\n", 0); in cadence_nand_setup_interface()
2580 dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2); in cadence_nand_setup_interface()
2581 dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n", in cadence_nand_setup_interface()
2583 t->phy_dqs_timing = dll_phy_dqs_timing; in cadence_nand_setup_interface()
2586 dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n", in cadence_nand_setup_interface()
2588 t->phy_gate_lpbk_ctrl = reg; in cadence_nand_setup_interface()
2590 dev_dbg(cdns_ctrl->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n", in cadence_nand_setup_interface()
2592 dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0); in cadence_nand_setup_interface()
2600 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_attach_chip()
2606 if (chip->options & NAND_BUSWIDTH_16) { in cadence_nand_attach_chip()
2612 chip->bbt_options |= NAND_BBT_USE_FLASH; in cadence_nand_attach_chip()
2613 chip->bbt_options |= NAND_BBT_NO_OOB; in cadence_nand_attach_chip()
2614 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in cadence_nand_attach_chip()
2616 chip->options |= NAND_NO_SUBPAGE_WRITE; in cadence_nand_attach_chip()
2618 cdns_chip->bbm_offs = chip->badblockpos; in cadence_nand_attach_chip()
2619 cdns_chip->bbm_offs &= ~0x01; in cadence_nand_attach_chip()
2621 cdns_chip->bbm_len = 2; in cadence_nand_attach_chip()
2624 &cdns_ctrl->ecc_caps, in cadence_nand_attach_chip()
2625 mtd->oobsize - cdns_chip->bbm_len); in cadence_nand_attach_chip()
2627 dev_err(cdns_ctrl->dev, "ECC configuration failed\n"); in cadence_nand_attach_chip()
2631 dev_dbg(cdns_ctrl->dev, in cadence_nand_attach_chip()
2632 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", in cadence_nand_attach_chip()
2633 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); in cadence_nand_attach_chip()
2636 cdns_chip->sector_size = chip->ecc.size; in cadence_nand_attach_chip()
2637 cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size; in cadence_nand_attach_chip()
2638 ecc_size = cdns_chip->sector_count * chip->ecc.bytes; in cadence_nand_attach_chip()
2640 cdns_chip->avail_oob_size = mtd->oobsize - ecc_size; in cadence_nand_attach_chip()
2642 if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size) in cadence_nand_attach_chip()
2643 cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size; in cadence_nand_attach_chip()
2645 if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size) in cadence_nand_attach_chip()
2646 > mtd->oobsize) in cadence_nand_attach_chip()
2647 cdns_chip->avail_oob_size -= 4; in cadence_nand_attach_chip()
2649 ret = cadence_nand_get_ecc_strength_idx(cdns_ctrl, chip->ecc.strength); in cadence_nand_attach_chip()
2651 return -EINVAL; in cadence_nand_attach_chip()
2653 cdns_chip->corr_str_idx = (u8)ret; in cadence_nand_attach_chip()
2658 return -ETIMEDOUT; in cadence_nand_attach_chip()
2661 cdns_chip->corr_str_idx); in cadence_nand_attach_chip()
2664 chip->ecc.strength); in cadence_nand_attach_chip()
2667 chip->ecc.read_page = cadence_nand_read_page; in cadence_nand_attach_chip()
2668 chip->ecc.read_page_raw = cadence_nand_read_page_raw; in cadence_nand_attach_chip()
2669 chip->ecc.write_page = cadence_nand_write_page; in cadence_nand_attach_chip()
2670 chip->ecc.write_page_raw = cadence_nand_write_page_raw; in cadence_nand_attach_chip()
2671 chip->ecc.read_oob = cadence_nand_read_oob; in cadence_nand_attach_chip()
2672 chip->ecc.write_oob = cadence_nand_write_oob; in cadence_nand_attach_chip()
2673 chip->ecc.read_oob_raw = cadence_nand_read_oob_raw; in cadence_nand_attach_chip()
2674 chip->ecc.write_oob_raw = cadence_nand_write_oob_raw; in cadence_nand_attach_chip()
2676 if ((mtd->writesize + mtd->oobsize) > cdns_ctrl->buf_size) in cadence_nand_attach_chip()
2677 cdns_ctrl->buf_size = mtd->writesize + mtd->oobsize; in cadence_nand_attach_chip()
2679 /* Is 32-bit DMA supported? */ in cadence_nand_attach_chip()
2680 ret = dma_set_mask(cdns_ctrl->dev, DMA_BIT_MASK(32)); in cadence_nand_attach_chip()
2682 dev_err(cdns_ctrl->dev, "no usable DMA configuration\n"); in cadence_nand_attach_chip()
2708 dev_err(cdns_ctrl->dev, "missing/invalid reg property\n"); in cadence_nand_chip_init()
2709 return -EINVAL; in cadence_nand_chip_init()
2712 /* Allocate the nand chip structure. */ in cadence_nand_chip_init()
2713 cdns_chip = devm_kzalloc(cdns_ctrl->dev, sizeof(*cdns_chip) + in cadence_nand_chip_init()
2717 dev_err(cdns_ctrl->dev, "could not allocate chip structure\n"); in cadence_nand_chip_init()
2718 return -ENOMEM; in cadence_nand_chip_init()
2721 cdns_chip->nsels = nsels; in cadence_nand_chip_init()
2727 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2733 if (cs >= cdns_ctrl->caps2.max_banks) { in cadence_nand_chip_init()
2734 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2736 cs, cdns_ctrl->caps2.max_banks); in cadence_nand_chip_init()
2737 return -EINVAL; in cadence_nand_chip_init()
2740 if (test_and_set_bit(cs, &cdns_ctrl->assigned_cs)) { in cadence_nand_chip_init()
2741 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2743 return -EINVAL; in cadence_nand_chip_init()
2746 cdns_chip->cs[i] = cs; in cadence_nand_chip_init()
2749 chip = &cdns_chip->chip; in cadence_nand_chip_init()
2750 chip->controller = &cdns_ctrl->controller; in cadence_nand_chip_init()
2754 mtd->dev.parent = cdns_ctrl->dev; in cadence_nand_chip_init()
2757 * Default to HW ECC engine mode. If the nand-ecc-mode property is given in cadence_nand_chip_init()
2760 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in cadence_nand_chip_init()
2762 ret = nand_scan(chip, cdns_chip->nsels); in cadence_nand_chip_init()
2764 dev_err(cdns_ctrl->dev, "could not scan the nand chip\n"); in cadence_nand_chip_init()
2770 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2776 list_add_tail(&cdns_chip->node, &cdns_ctrl->chips); in cadence_nand_chip_init()
2787 list_for_each_entry_safe(entry, temp, &cdns_ctrl->chips, node) { in cadence_nand_chips_cleanup()
2788 chip = &entry->chip; in cadence_nand_chips_cleanup()
2792 list_del(&entry->node); in cadence_nand_chips_cleanup()
2798 struct device_node *np = cdns_ctrl->dev->of_node; in cadence_nand_chips_init()
2800 int max_cs = cdns_ctrl->caps2.max_banks; in cadence_nand_chips_init()
2806 dev_err(cdns_ctrl->dev, in cadence_nand_chips_init()
2807 "too many NAND chips: %d (max = %d CS)\n", in cadence_nand_chips_init()
2809 return -EINVAL; in cadence_nand_chips_init()
2828 writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_irq_cleanup()
2836 cdns_ctrl->cdma_desc = dma_alloc_coherent(cdns_ctrl->dev, in cadence_nand_init()
2837 sizeof(*cdns_ctrl->cdma_desc), in cadence_nand_init()
2838 &cdns_ctrl->dma_cdma_desc, in cadence_nand_init()
2840 if (!cdns_ctrl->dma_cdma_desc) in cadence_nand_init()
2841 return -ENOMEM; in cadence_nand_init()
2843 cdns_ctrl->buf_size = SZ_16K; in cadence_nand_init()
2844 cdns_ctrl->buf = kmalloc(cdns_ctrl->buf_size, GFP_KERNEL); in cadence_nand_init()
2845 if (!cdns_ctrl->buf) { in cadence_nand_init()
2846 ret = -ENOMEM; in cadence_nand_init()
2850 if (devm_request_irq(cdns_ctrl->dev, cdns_ctrl->irq, cadence_nand_isr, in cadence_nand_init()
2851 IRQF_SHARED, "cadence-nand-controller", in cadence_nand_init()
2853 dev_err(cdns_ctrl->dev, "Unable to allocate IRQ\n"); in cadence_nand_init()
2854 ret = -ENODEV; in cadence_nand_init()
2858 spin_lock_init(&cdns_ctrl->irq_lock); in cadence_nand_init()
2859 init_completion(&cdns_ctrl->complete); in cadence_nand_init()
2868 if (cdns_ctrl->caps1->has_dma) { in cadence_nand_init()
2869 cdns_ctrl->dmac = dma_request_channel(mask, NULL, NULL); in cadence_nand_init()
2870 if (!cdns_ctrl->dmac) { in cadence_nand_init()
2871 dev_err(cdns_ctrl->dev, in cadence_nand_init()
2873 ret = -EBUSY; in cadence_nand_init()
2878 nand_controller_init(&cdns_ctrl->controller); in cadence_nand_init()
2879 INIT_LIST_HEAD(&cdns_ctrl->chips); in cadence_nand_init()
2881 cdns_ctrl->controller.ops = &cadence_nand_controller_ops; in cadence_nand_init()
2882 cdns_ctrl->curr_corr_str_idx = 0xFF; in cadence_nand_init()
2886 dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n", in cadence_nand_init()
2891 kfree(cdns_ctrl->buf); in cadence_nand_init()
2892 cdns_ctrl->buf = kzalloc(cdns_ctrl->buf_size, GFP_KERNEL); in cadence_nand_init()
2893 if (!cdns_ctrl->buf) { in cadence_nand_init()
2894 ret = -ENOMEM; in cadence_nand_init()
2901 if (cdns_ctrl->dmac) in cadence_nand_init()
2902 dma_release_channel(cdns_ctrl->dmac); in cadence_nand_init()
2905 cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); in cadence_nand_init()
2908 kfree(cdns_ctrl->buf); in cadence_nand_init()
2911 dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), in cadence_nand_init()
2912 cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc); in cadence_nand_init()
2921 cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); in cadence_nand_remove()
2922 kfree(cdns_ctrl->buf); in cadence_nand_remove()
2923 dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), in cadence_nand_remove()
2924 cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc); in cadence_nand_remove()
2926 if (cdns_ctrl->dmac) in cadence_nand_remove()
2927 dma_release_channel(cdns_ctrl->dmac); in cadence_nand_remove()
2942 .compatible = "cdns,hp-nfc",
2959 of_id = of_match_device(cadence_nand_dt_ids, &ofdev->dev); in cadence_nand_dt_probe()
2961 ofdev->id_entry = of_id->data; in cadence_nand_dt_probe()
2962 devdata = of_id->data; in cadence_nand_dt_probe()
2965 return -ENOMEM; in cadence_nand_dt_probe()
2968 dt = devm_kzalloc(&ofdev->dev, sizeof(*dt), GFP_KERNEL); in cadence_nand_dt_probe()
2970 return -ENOMEM; in cadence_nand_dt_probe()
2972 cdns_ctrl = &dt->cdns_ctrl; in cadence_nand_dt_probe()
2973 cdns_ctrl->caps1 = devdata; in cadence_nand_dt_probe()
2975 cdns_ctrl->dev = &ofdev->dev; in cadence_nand_dt_probe()
2976 cdns_ctrl->irq = platform_get_irq(ofdev, 0); in cadence_nand_dt_probe()
2977 if (cdns_ctrl->irq < 0) in cadence_nand_dt_probe()
2978 return cdns_ctrl->irq; in cadence_nand_dt_probe()
2980 dev_info(cdns_ctrl->dev, "IRQ: nr %d\n", cdns_ctrl->irq); in cadence_nand_dt_probe()
2982 cdns_ctrl->reg = devm_platform_ioremap_resource(ofdev, 0); in cadence_nand_dt_probe()
2983 if (IS_ERR(cdns_ctrl->reg)) in cadence_nand_dt_probe()
2984 return PTR_ERR(cdns_ctrl->reg); in cadence_nand_dt_probe()
2987 cdns_ctrl->io.dma = res->start; in cadence_nand_dt_probe()
2988 cdns_ctrl->io.virt = devm_ioremap_resource(&ofdev->dev, res); in cadence_nand_dt_probe()
2989 if (IS_ERR(cdns_ctrl->io.virt)) in cadence_nand_dt_probe()
2990 return PTR_ERR(cdns_ctrl->io.virt); in cadence_nand_dt_probe()
2992 dt->clk = devm_clk_get(cdns_ctrl->dev, "nf_clk"); in cadence_nand_dt_probe()
2993 if (IS_ERR(dt->clk)) in cadence_nand_dt_probe()
2994 return PTR_ERR(dt->clk); in cadence_nand_dt_probe()
2996 cdns_ctrl->nf_clk_rate = clk_get_rate(dt->clk); in cadence_nand_dt_probe()
2998 ret = of_property_read_u32(ofdev->dev.of_node, in cadence_nand_dt_probe()
2999 "cdns,board-delay-ps", &val); in cadence_nand_dt_probe()
3002 dev_info(cdns_ctrl->dev, in cadence_nand_dt_probe()
3003 "missing cdns,board-delay-ps property, %d was set\n", in cadence_nand_dt_probe()
3006 cdns_ctrl->board_delay = val; in cadence_nand_dt_probe()
3020 cadence_nand_remove(&dt->cdns_ctrl); in cadence_nand_dt_remove()
3029 .name = "cadence-nand-controller",
3038 MODULE_DESCRIPTION("Driver for Cadence NAND flash controller");