Lines Matching +full:nand +full:- +full:rb
1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
65 #include <soc/at91/atmel-sfr.h>
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
150 struct atmel_nand_rb rb; member
201 struct atmel_nand *nand);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
205 int (*exec_op)(struct atmel_nand *nand,
280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; in atmel_nfc_op_done()
281 op->wait ^= status & op->wait; in atmel_nfc_op_done()
283 return !op->wait || op->errors; in atmel_nfc_op_done()
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); in atmel_nfc_interrupt()
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_interrupt()
295 done = atmel_nfc_op_done(&nc->op, sr); in atmel_nfc_interrupt()
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); in atmel_nfc_interrupt()
301 complete(&nc->complete); in atmel_nfc_interrupt()
317 ret = regmap_read_poll_timeout(nc->base.smc, in atmel_nfc_wait()
319 atmel_nfc_op_done(&nc->op, in atmel_nfc_wait()
323 init_completion(&nc->complete); in atmel_nfc_wait()
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, in atmel_nfc_wait()
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_wait()
326 ret = wait_for_completion_timeout(&nc->complete, in atmel_nfc_wait()
329 ret = -ETIMEDOUT; in atmel_nfc_wait()
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_nfc_wait()
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { in atmel_nfc_wait()
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
338 ret = -ETIMEDOUT; in atmel_nfc_wait()
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { in atmel_nfc_wait()
342 dev_err(nc->base.dev, "Access to an undefined area\n"); in atmel_nfc_wait()
343 ret = -EIO; in atmel_nfc_wait()
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { in atmel_nfc_wait()
347 dev_err(nc->base.dev, "Access while busy\n"); in atmel_nfc_wait()
348 ret = -EIO; in atmel_nfc_wait()
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { in atmel_nfc_wait()
352 dev_err(nc->base.dev, "Wrong access size\n"); in atmel_nfc_wait()
353 ret = -EIO; in atmel_nfc_wait()
375 buf_dma = dma_map_single(nc->dev, buf, len, dir); in atmel_nand_dma_transfer()
376 if (dma_mapping_error(nc->dev, dev_dma)) { in atmel_nand_dma_transfer()
377 dev_err(nc->dev, in atmel_nand_dma_transfer()
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len, in atmel_nand_dma_transfer()
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n"); in atmel_nand_dma_transfer()
397 tx->callback = atmel_nand_dma_transfer_finished; in atmel_nand_dma_transfer()
398 tx->callback_param = &finished; in atmel_nand_dma_transfer()
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n"); in atmel_nand_dma_transfer()
406 dma_async_issue_pending(nc->dmac); in atmel_nand_dma_transfer()
412 dma_unmap_single(nc->dev, buf_dma, len, dir); in atmel_nand_dma_transfer()
415 dev_dbg(nc->dev, "Fall back to CPU I/O\n"); in atmel_nand_dma_transfer()
417 return -EIO; in atmel_nand_dma_transfer()
422 u8 *addrs = nc->op.addrs; in atmel_nfc_exec_op()
427 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; in atmel_nfc_exec_op()
429 for (i = 0; i < nc->op.ncmds; i++) in atmel_nfc_exec_op()
430 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); in atmel_nfc_exec_op()
432 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) in atmel_nfc_exec_op()
433 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); in atmel_nfc_exec_op()
435 op |= ATMEL_NFC_CSID(nc->op.cs) | in atmel_nfc_exec_op()
436 ATMEL_NFC_ACYCLE(nc->op.naddrs); in atmel_nfc_exec_op()
438 if (nc->op.ncmds > 1) in atmel_nfc_exec_op()
444 if (nc->op.data != ATMEL_NFC_NO_DATA) { in atmel_nfc_exec_op()
446 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; in atmel_nfc_exec_op()
448 if (nc->op.data == ATMEL_NFC_WRITE_DATA) in atmel_nfc_exec_op()
453 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); in atmel_nfc_exec_op()
456 regmap_write(nc->io, op, addr); in atmel_nfc_exec_op()
460 dev_err(nc->base.dev, in atmel_nfc_exec_op()
461 "Failed to send NAND command (err = %d)!", in atmel_nfc_exec_op()
465 memset(&nc->op, 0, sizeof(nc->op)); in atmel_nfc_exec_op()
470 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, in atmel_nand_data_in() argument
475 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_in()
478 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_in()
482 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_in()
484 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, in atmel_nand_data_in()
488 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_in()
489 ioread16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_in()
491 ioread8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_in()
494 static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf, in atmel_nand_data_out() argument
499 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_out()
502 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_out()
506 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_out()
508 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, in atmel_nand_data_out()
512 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_out()
513 iowrite16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_out()
515 iowrite8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_out()
518 static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms) in atmel_nand_waitrdy() argument
520 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB) in atmel_nand_waitrdy()
521 return nand_soft_waitrdy(&nand->base, timeout_ms); in atmel_nand_waitrdy()
523 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio, in atmel_nand_waitrdy()
527 static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand, in atmel_hsmc_nand_waitrdy() argument
533 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_waitrdy()
534 return atmel_nand_waitrdy(nand, timeout_ms); in atmel_hsmc_nand_waitrdy()
536 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_waitrdy()
537 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); in atmel_hsmc_nand_waitrdy()
538 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR, in atmel_hsmc_nand_waitrdy()
543 static void atmel_nand_select_target(struct atmel_nand *nand, in atmel_nand_select_target() argument
546 nand->activecs = &nand->cs[cs]; in atmel_nand_select_target()
549 static void atmel_hsmc_nand_select_target(struct atmel_nand *nand, in atmel_hsmc_nand_select_target() argument
552 struct mtd_info *mtd = nand_to_mtd(&nand->base); in atmel_hsmc_nand_select_target()
554 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | in atmel_hsmc_nand_select_target()
555 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | in atmel_hsmc_nand_select_target()
558 nand->activecs = &nand->cs[cs]; in atmel_hsmc_nand_select_target()
559 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_select_target()
560 if (nc->cfg == cfg) in atmel_hsmc_nand_select_target()
563 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_select_target()
569 nc->cfg = cfg; in atmel_hsmc_nand_select_target()
572 static int atmel_smc_nand_exec_instr(struct atmel_nand *nand, in atmel_smc_nand_exec_instr() argument
578 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_exec_instr()
579 switch (instr->type) { in atmel_smc_nand_exec_instr()
581 writeb(instr->ctx.cmd.opcode, in atmel_smc_nand_exec_instr()
582 nand->activecs->io.virt + nc->caps->cle_offs); in atmel_smc_nand_exec_instr()
585 for (i = 0; i < instr->ctx.addr.naddrs; i++) in atmel_smc_nand_exec_instr()
586 writeb(instr->ctx.addr.addrs[i], in atmel_smc_nand_exec_instr()
587 nand->activecs->io.virt + nc->caps->ale_offs); in atmel_smc_nand_exec_instr()
590 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_smc_nand_exec_instr()
591 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
592 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
595 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_smc_nand_exec_instr()
596 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
597 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
600 return atmel_nand_waitrdy(nand, in atmel_smc_nand_exec_instr()
601 instr->ctx.waitrdy.timeout_ms); in atmel_smc_nand_exec_instr()
606 return -EINVAL; in atmel_smc_nand_exec_instr()
609 static int atmel_smc_nand_exec_op(struct atmel_nand *nand, in atmel_smc_nand_exec_op() argument
619 atmel_nand_select_target(nand, op->cs); in atmel_smc_nand_exec_op()
620 gpiod_set_value(nand->activecs->csgpio, 0); in atmel_smc_nand_exec_op()
621 for (i = 0; i < op->ninstrs; i++) { in atmel_smc_nand_exec_op()
622 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); in atmel_smc_nand_exec_op()
626 gpiod_set_value(nand->activecs->csgpio, 1); in atmel_smc_nand_exec_op()
634 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_cmd_addr() local
638 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_exec_cmd_addr()
640 nc->op.cs = nand->activecs->id; in atmel_hsmc_exec_cmd_addr()
641 for (i = 0; i < subop->ninstrs; i++) { in atmel_hsmc_exec_cmd_addr()
642 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
644 if (instr->type == NAND_OP_CMD_INSTR) { in atmel_hsmc_exec_cmd_addr()
645 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode; in atmel_hsmc_exec_cmd_addr()
651 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j]; in atmel_hsmc_exec_cmd_addr()
652 nc->op.naddrs++; in atmel_hsmc_exec_cmd_addr()
662 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
663 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_rw() local
665 if (instr->type == NAND_OP_DATA_IN_INSTR) in atmel_hsmc_exec_rw()
666 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_hsmc_exec_rw()
667 instr->ctx.data.len, in atmel_hsmc_exec_rw()
668 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
670 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_hsmc_exec_rw()
671 instr->ctx.data.len, in atmel_hsmc_exec_rw()
672 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
680 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()
681 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_waitrdy() local
683 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms); in atmel_hsmc_exec_waitrdy()
699 static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand, in atmel_hsmc_nand_exec_op() argument
706 return nand_op_parser_exec_op(&nand->base, in atmel_hsmc_nand_exec_op()
709 atmel_hsmc_nand_select_target(nand, op->cs); in atmel_hsmc_nand_exec_op()
710 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op, in atmel_hsmc_nand_exec_op()
721 int ret = -EIO; in atmel_nfc_copy_to_sram()
723 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_to_sram()
725 if (nc->base.dmac) in atmel_nfc_copy_to_sram()
726 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, in atmel_nfc_copy_to_sram()
727 nc->sram.dma, mtd->writesize, in atmel_nfc_copy_to_sram()
732 memcpy_toio(nc->sram.virt, buf, mtd->writesize); in atmel_nfc_copy_to_sram()
735 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, in atmel_nfc_copy_to_sram()
736 mtd->oobsize); in atmel_nfc_copy_to_sram()
744 int ret = -EIO; in atmel_nfc_copy_from_sram()
746 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_from_sram()
748 if (nc->base.dmac) in atmel_nfc_copy_from_sram()
749 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, in atmel_nfc_copy_from_sram()
750 mtd->writesize, DMA_FROM_DEVICE); in atmel_nfc_copy_from_sram()
754 memcpy_fromio(buf, nc->sram.virt, mtd->writesize); in atmel_nfc_copy_from_sram()
757 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, in atmel_nfc_copy_from_sram()
758 mtd->oobsize); in atmel_nfc_copy_from_sram()
766 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_set_op_addr()
769 nc->op.addrs[nc->op.naddrs++] = column; in atmel_nfc_set_op_addr()
774 if (mtd->writesize > 512) in atmel_nfc_set_op_addr()
775 nc->op.addrs[nc->op.naddrs++] = column >> 8; in atmel_nfc_set_op_addr()
779 nc->op.addrs[nc->op.naddrs++] = page; in atmel_nfc_set_op_addr()
780 nc->op.addrs[nc->op.naddrs++] = page >> 8; in atmel_nfc_set_op_addr()
782 if (chip->options & NAND_ROW_ADDR_3) in atmel_nfc_set_op_addr()
783 nc->op.addrs[nc->op.naddrs++] = page >> 16; in atmel_nfc_set_op_addr()
789 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_enable() local
793 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_enable()
798 ret = atmel_pmecc_enable(nand->pmecc, op); in atmel_nand_pmecc_enable()
800 dev_err(nc->dev, in atmel_nand_pmecc_enable()
808 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_disable() local
811 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_disable()
816 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_generate_eccbytes() local
823 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_generate_eccbytes()
828 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_generate_eccbytes()
830 dev_err(nc->dev, in atmel_nand_pmecc_generate_eccbytes()
831 "Failed to transfer NAND page data (err = %d)\n", in atmel_nand_pmecc_generate_eccbytes()
837 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_generate_eccbytes()
839 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_generate_eccbytes()
840 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, in atmel_nand_pmecc_generate_eccbytes()
842 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_generate_eccbytes()
851 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_correct_data() local
858 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_correct_data()
863 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_correct_data()
865 dev_err(nc->dev, in atmel_nand_pmecc_correct_data()
866 "Failed to read NAND page data (err = %d)\n", in atmel_nand_pmecc_correct_data()
872 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_correct_data()
875 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_correct_data()
876 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, in atmel_nand_pmecc_correct_data()
878 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) in atmel_nand_pmecc_correct_data()
880 chip->ecc.size, in atmel_nand_pmecc_correct_data()
882 chip->ecc.bytes, in atmel_nand_pmecc_correct_data()
884 chip->ecc.strength); in atmel_nand_pmecc_correct_data()
889 mtd->ecc_stats.failed++; in atmel_nand_pmecc_correct_data()
891 databuf += chip->ecc.size; in atmel_nand_pmecc_correct_data()
892 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_correct_data()
902 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_write_pg() local
911 nand_write_data_op(chip, buf, mtd->writesize, false); in atmel_nand_pmecc_write_pg()
915 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_write_pg()
921 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_nand_pmecc_write_pg()
951 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false); in atmel_nand_pmecc_read_pg()
955 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false); in atmel_nand_pmecc_read_pg()
984 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_write_pg() local
988 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_write_pg()
989 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_write_pg()
993 nc->op.cmds[0] = NAND_CMD_SEQIN; in atmel_hsmc_nand_pmecc_write_pg()
994 nc->op.ncmds = 1; in atmel_hsmc_nand_pmecc_write_pg()
996 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_write_pg()
997 nc->op.data = ATMEL_NFC_WRITE_DATA; in atmel_hsmc_nand_pmecc_write_pg()
1006 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_write_pg()
1007 "Failed to transfer NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_write_pg()
1019 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_hsmc_nand_pmecc_write_pg()
1045 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_read_pg() local
1049 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_read_pg()
1050 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_read_pg()
1053 * Optimized read page accessors only work when the NAND R/B pin is in atmel_hsmc_nand_pmecc_read_pg()
1055 * to the non-optimized one. in atmel_hsmc_nand_pmecc_read_pg()
1057 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_pmecc_read_pg()
1061 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; in atmel_hsmc_nand_pmecc_read_pg()
1063 if (mtd->writesize > 512) in atmel_hsmc_nand_pmecc_read_pg()
1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; in atmel_hsmc_nand_pmecc_read_pg()
1067 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_read_pg()
1068 nc->op.data = ATMEL_NFC_READ_DATA; in atmel_hsmc_nand_pmecc_read_pg()
1077 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_read_pg()
1078 "Failed to load NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_read_pg()
1110 nanddev_get_ecc_requirements(&chip->base); in atmel_nand_pmecc_init()
1113 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_init() local
1117 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_init()
1119 if (!nc->pmecc) { in atmel_nand_pmecc_init()
1120 dev_err(nc->dev, "HW ECC not supported\n"); in atmel_nand_pmecc_init()
1121 return -ENOTSUPP; in atmel_nand_pmecc_init()
1124 if (nc->caps->legacy_of_bindings) { in atmel_nand_pmecc_init()
1127 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap", in atmel_nand_pmecc_init()
1129 chip->ecc.strength = val; in atmel_nand_pmecc_init()
1131 if (!of_property_read_u32(nc->dev->of_node, in atmel_nand_pmecc_init()
1132 "atmel,pmecc-sector-size", in atmel_nand_pmecc_init()
1134 chip->ecc.size = val; in atmel_nand_pmecc_init()
1137 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in atmel_nand_pmecc_init()
1139 else if (chip->ecc.strength) in atmel_nand_pmecc_init()
1140 req.ecc.strength = chip->ecc.strength; in atmel_nand_pmecc_init()
1141 else if (requirements->strength) in atmel_nand_pmecc_init()
1142 req.ecc.strength = requirements->strength; in atmel_nand_pmecc_init()
1146 if (chip->ecc.size) in atmel_nand_pmecc_init()
1147 req.ecc.sectorsize = chip->ecc.size; in atmel_nand_pmecc_init()
1148 else if (requirements->step_size) in atmel_nand_pmecc_init()
1149 req.ecc.sectorsize = requirements->step_size; in atmel_nand_pmecc_init()
1153 req.pagesize = mtd->writesize; in atmel_nand_pmecc_init()
1154 req.oobsize = mtd->oobsize; in atmel_nand_pmecc_init()
1156 if (mtd->writesize <= 512) { in atmel_nand_pmecc_init()
1160 req.ecc.bytes = mtd->oobsize - 2; in atmel_nand_pmecc_init()
1164 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); in atmel_nand_pmecc_init()
1165 if (IS_ERR(nand->pmecc)) in atmel_nand_pmecc_init()
1166 return PTR_ERR(nand->pmecc); in atmel_nand_pmecc_init()
1168 chip->ecc.algo = NAND_ECC_ALGO_BCH; in atmel_nand_pmecc_init()
1169 chip->ecc.size = req.ecc.sectorsize; in atmel_nand_pmecc_init()
1170 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; in atmel_nand_pmecc_init()
1171 chip->ecc.strength = req.ecc.strength; in atmel_nand_pmecc_init()
1173 chip->options |= NAND_NO_SUBPAGE_WRITE; in atmel_nand_pmecc_init()
1185 nc = to_nand_controller(chip->controller); in atmel_nand_ecc_init()
1187 switch (chip->ecc.engine_type) { in atmel_nand_ecc_init()
1200 chip->ecc.read_page = atmel_nand_pmecc_read_page; in atmel_nand_ecc_init()
1201 chip->ecc.write_page = atmel_nand_pmecc_write_page; in atmel_nand_ecc_init()
1202 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; in atmel_nand_ecc_init()
1203 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; in atmel_nand_ecc_init()
1208 dev_err(nc->dev, "Unsupported ECC mode: %d\n", in atmel_nand_ecc_init()
1209 chip->ecc.engine_type); in atmel_nand_ecc_init()
1210 return -ENOTSUPP; in atmel_nand_ecc_init()
1224 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in atmel_hsmc_nand_ecc_init()
1228 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; in atmel_hsmc_nand_ecc_init()
1229 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; in atmel_hsmc_nand_ecc_init()
1230 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; in atmel_hsmc_nand_ecc_init()
1231 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; in atmel_hsmc_nand_ecc_init()
1236 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, in atmel_smc_nand_prepare_smcconf() argument
1244 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_prepare_smcconf()
1247 if (conf->type != NAND_SDR_IFACE) in atmel_smc_nand_prepare_smcconf()
1248 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1254 if (conf->timings.sdr.tRC_min < 30000) in atmel_smc_nand_prepare_smcconf()
1255 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1259 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); in atmel_smc_nand_prepare_smcconf()
1267 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1275 * The write setup timing depends on the operation done on the NAND. in atmel_smc_nand_prepare_smcconf()
1283 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE in atmel_smc_nand_prepare_smcconf()
1285 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, in atmel_smc_nand_prepare_smcconf()
1286 conf->timings.sdr.tALS_min); in atmel_smc_nand_prepare_smcconf()
1287 timeps = max(timeps, conf->timings.sdr.tDS_min); in atmel_smc_nand_prepare_smcconf()
1289 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; in atmel_smc_nand_prepare_smcconf()
1298 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1302 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, in atmel_smc_nand_prepare_smcconf()
1303 conf->timings.sdr.tALH_min); in atmel_smc_nand_prepare_smcconf()
1304 timeps = max3(timeps, conf->timings.sdr.tDH_min, in atmel_smc_nand_prepare_smcconf()
1305 conf->timings.sdr.tWH_min); in atmel_smc_nand_prepare_smcconf()
1316 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1325 * transfer to the NAND. The only way to guarantee that is to have the in atmel_smc_nand_prepare_smcconf()
1337 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1341 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); in atmel_smc_nand_prepare_smcconf()
1346 * TDF = tRHZ - NRD_HOLD in atmel_smc_nand_prepare_smcconf()
1348 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1349 ncycles -= totalcycles; in atmel_smc_nand_prepare_smcconf()
1354 * Just take the max value in this case and hope that the NAND is more in atmel_smc_nand_prepare_smcconf()
1362 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | in atmel_smc_nand_prepare_smcconf()
1370 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1386 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1395 * transfer from the NAND. The only way to guarantee that is to have in atmel_smc_nand_prepare_smcconf()
1406 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1413 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1421 * accept the -ERANGE return code. in atmel_smc_nand_prepare_smcconf()
1428 if (ret && ret != -ERANGE) in atmel_smc_nand_prepare_smcconf()
1431 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1438 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1445 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1453 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; in atmel_smc_nand_prepare_smcconf()
1456 if (nand->base.options & NAND_BUSWIDTH_16) in atmel_smc_nand_prepare_smcconf()
1457 smcconf->mode |= ATMEL_SMC_MODE_DBW_16; in atmel_smc_nand_prepare_smcconf()
1460 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | in atmel_smc_nand_prepare_smcconf()
1466 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand, in atmel_smc_nand_setup_interface() argument
1475 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_setup_interface()
1477 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_smc_nand_setup_interface()
1484 cs = &nand->cs[csline]; in atmel_smc_nand_setup_interface()
1485 cs->smcconf = smcconf; in atmel_smc_nand_setup_interface()
1486 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); in atmel_smc_nand_setup_interface()
1491 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand, in atmel_hsmc_nand_setup_interface() argument
1500 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_setup_interface()
1502 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_hsmc_nand_setup_interface()
1509 cs = &nand->cs[csline]; in atmel_hsmc_nand_setup_interface()
1510 cs->smcconf = smcconf; in atmel_hsmc_nand_setup_interface()
1512 if (cs->rb.type == ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_setup_interface()
1513 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); in atmel_hsmc_nand_setup_interface()
1515 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, in atmel_hsmc_nand_setup_interface()
1516 &cs->smcconf); in atmel_hsmc_nand_setup_interface()
1524 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_setup_interface() local
1527 nc = to_nand_controller(nand->base.controller); in atmel_nand_setup_interface()
1529 if (csline >= nand->numcs || in atmel_nand_setup_interface()
1531 return -EINVAL; in atmel_nand_setup_interface()
1533 return nc->caps->ops->setup_interface(nand, csline, conf); in atmel_nand_setup_interface()
1540 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_exec_op() local
1543 nc = to_nand_controller(nand->base.controller); in atmel_nand_exec_op()
1545 return nc->caps->ops->exec_op(nand, op, check_only); in atmel_nand_exec_op()
1549 struct atmel_nand *nand) in atmel_nand_init() argument
1551 struct nand_chip *chip = &nand->base; in atmel_nand_init()
1554 mtd->dev.parent = nc->dev; in atmel_nand_init()
1555 nand->base.controller = &nc->base; in atmel_nand_init()
1557 if (!nc->mck || !nc->caps->ops->setup_interface) in atmel_nand_init()
1558 chip->options |= NAND_KEEP_TIMINGS; in atmel_nand_init()
1564 if (nc->dmac) in atmel_nand_init()
1565 chip->options |= NAND_USES_DMA; in atmel_nand_init()
1568 if (nc->pmecc) in atmel_nand_init()
1569 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in atmel_nand_init()
1573 struct atmel_nand *nand) in atmel_smc_nand_init() argument
1575 struct nand_chip *chip = &nand->base; in atmel_smc_nand_init()
1579 atmel_nand_init(nc, nand); in atmel_smc_nand_init()
1581 smc_nc = to_smc_nand_controller(chip->controller); in atmel_smc_nand_init()
1582 if (!smc_nc->ebi_csa_regmap) in atmel_smc_nand_init()
1585 /* Attach the CS to the NAND Flash logic. */ in atmel_smc_nand_init()
1586 for (i = 0; i < nand->numcs; i++) in atmel_smc_nand_init()
1587 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1588 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1589 BIT(nand->cs[i].id), BIT(nand->cs[i].id)); in atmel_smc_nand_init()
1591 if (smc_nc->ebi_csa->nfd0_on_d16) in atmel_smc_nand_init()
1592 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1593 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1594 smc_nc->ebi_csa->nfd0_on_d16, in atmel_smc_nand_init()
1595 smc_nc->ebi_csa->nfd0_on_d16); in atmel_smc_nand_init()
1598 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) in atmel_nand_controller_remove_nand() argument
1600 struct nand_chip *chip = &nand->base; in atmel_nand_controller_remove_nand()
1609 list_del(&nand->node); in atmel_nand_controller_remove_nand()
1618 struct atmel_nand *nand; in atmel_nand_create() local
1625 dev_err(nc->dev, "Missing or invalid reg property\n"); in atmel_nand_create()
1626 return ERR_PTR(-EINVAL); in atmel_nand_create()
1629 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL); in atmel_nand_create()
1630 if (!nand) { in atmel_nand_create()
1631 dev_err(nc->dev, "Failed to allocate NAND object\n"); in atmel_nand_create()
1632 return ERR_PTR(-ENOMEM); in atmel_nand_create()
1635 nand->numcs = numcs; in atmel_nand_create()
1637 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np), in atmel_nand_create()
1638 "det", GPIOD_IN, "nand-det"); in atmel_nand_create()
1639 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1640 dev_err(nc->dev, in atmel_nand_create()
1647 nand->cdgpio = gpio; in atmel_nand_create()
1655 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1663 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1668 nand->cs[i].id = val; in atmel_nand_create()
1670 nand->cs[i].io.dma = res.start; in atmel_nand_create()
1671 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res); in atmel_nand_create()
1672 if (IS_ERR(nand->cs[i].io.virt)) in atmel_nand_create()
1673 return ERR_CAST(nand->cs[i].io.virt); in atmel_nand_create()
1675 if (!of_property_read_u32(np, "atmel,rb", &val)) { in atmel_nand_create()
1677 return ERR_PTR(-EINVAL); in atmel_nand_create()
1679 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; in atmel_nand_create()
1680 nand->cs[i].rb.id = val; in atmel_nand_create()
1682 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1684 "rb", i, GPIOD_IN, in atmel_nand_create()
1685 "nand-rb"); in atmel_nand_create()
1686 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1687 dev_err(nc->dev, in atmel_nand_create()
1694 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_create()
1695 nand->cs[i].rb.gpio = gpio; in atmel_nand_create()
1699 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1702 "nand-cs"); in atmel_nand_create()
1703 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1704 dev_err(nc->dev, in atmel_nand_create()
1711 nand->cs[i].csgpio = gpio; in atmel_nand_create()
1714 nand_set_flash_node(&nand->base, np); in atmel_nand_create()
1716 return nand; in atmel_nand_create()
1721 struct atmel_nand *nand) in atmel_nand_controller_add_nand() argument
1723 struct nand_chip *chip = &nand->base; in atmel_nand_controller_add_nand()
1727 /* No card inserted, skip this NAND. */ in atmel_nand_controller_add_nand()
1728 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) { in atmel_nand_controller_add_nand()
1729 dev_info(nc->dev, "No SmartMedia card inserted.\n"); in atmel_nand_controller_add_nand()
1733 nc->caps->ops->nand_init(nc, nand); in atmel_nand_controller_add_nand()
1735 ret = nand_scan(chip, nand->numcs); in atmel_nand_controller_add_nand()
1737 dev_err(nc->dev, "NAND scan failed: %d\n", ret); in atmel_nand_controller_add_nand()
1743 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret); in atmel_nand_controller_add_nand()
1748 list_add_tail(&nand->node, &nc->chips); in atmel_nand_controller_add_nand()
1756 struct atmel_nand *nand, *tmp; in atmel_nand_controller_remove_nands() local
1759 list_for_each_entry_safe(nand, tmp, &nc->chips, node) { in atmel_nand_controller_remove_nands()
1760 ret = atmel_nand_controller_remove_nand(nand); in atmel_nand_controller_remove_nands()
1771 struct device *dev = nc->dev; in atmel_nand_controller_legacy_add_nands()
1773 struct atmel_nand *nand; in atmel_nand_controller_legacy_add_nands() local
1778 * Legacy bindings only allow connecting a single NAND with a unique CS in atmel_nand_controller_legacy_add_nands()
1781 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs), in atmel_nand_controller_legacy_add_nands()
1783 if (!nand) in atmel_nand_controller_legacy_add_nands()
1784 return -ENOMEM; in atmel_nand_controller_legacy_add_nands()
1786 nand->numcs = 1; in atmel_nand_controller_legacy_add_nands()
1789 nand->cs[0].io.virt = devm_ioremap_resource(dev, res); in atmel_nand_controller_legacy_add_nands()
1790 if (IS_ERR(nand->cs[0].io.virt)) in atmel_nand_controller_legacy_add_nands()
1791 return PTR_ERR(nand->cs[0].io.virt); in atmel_nand_controller_legacy_add_nands()
1793 nand->cs[0].io.dma = res->start; in atmel_nand_controller_legacy_add_nands()
1800 * If one wants to connect a NAND to a different CS line, he will in atmel_nand_controller_legacy_add_nands()
1803 nand->cs[0].id = 3; in atmel_nand_controller_legacy_add_nands()
1814 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_controller_legacy_add_nands()
1815 nand->cs[0].rb.gpio = gpio; in atmel_nand_controller_legacy_add_nands()
1826 nand->cs[0].csgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1829 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN); in atmel_nand_controller_legacy_add_nands()
1837 nand->cdgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1839 nand_set_flash_node(&nand->base, nc->dev->of_node); in atmel_nand_controller_legacy_add_nands()
1841 return atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_legacy_add_nands()
1847 struct device *dev = nc->dev; in atmel_nand_controller_add_nands()
1852 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_add_nands()
1855 np = dev->of_node; in atmel_nand_controller_add_nands()
1857 ret = of_property_read_u32(np, "#address-cells", &val); in atmel_nand_controller_add_nands()
1859 dev_err(dev, "missing #address-cells property\n"); in atmel_nand_controller_add_nands()
1865 ret = of_property_read_u32(np, "#size-cells", &val); in atmel_nand_controller_add_nands()
1867 dev_err(dev, "missing #size-cells property\n"); in atmel_nand_controller_add_nands()
1874 struct atmel_nand *nand; in atmel_nand_controller_add_nands() local
1876 nand = atmel_nand_create(nc, nand_np, reg_cells); in atmel_nand_controller_add_nands()
1877 if (IS_ERR(nand)) { in atmel_nand_controller_add_nands()
1878 ret = PTR_ERR(nand); in atmel_nand_controller_add_nands()
1882 ret = atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_add_nands()
1897 if (nc->dmac) in atmel_nand_controller_cleanup()
1898 dma_release_channel(nc->dmac); in atmel_nand_controller_cleanup()
1900 clk_put(nc->mck); in atmel_nand_controller_cleanup()
1938 .compatible = "atmel,at91sam9260-matrix",
1942 .compatible = "atmel,at91sam9261-matrix",
1946 .compatible = "atmel,at91sam9263-matrix",
1950 .compatible = "atmel,at91sam9rl-matrix",
1954 .compatible = "atmel,at91sam9g45-matrix",
1958 .compatible = "atmel,at91sam9n12-matrix",
1962 .compatible = "atmel,at91sam9x5-matrix",
1966 .compatible = "microchip,sam9x60-sfr",
1974 struct atmel_nand_controller *nc = to_nand_controller(chip->controller); in atmel_nand_attach_chip()
1975 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_attach_chip() local
1979 ret = nc->caps->ops->ecc_init(chip); in atmel_nand_attach_chip()
1983 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) { in atmel_nand_attach_chip()
1989 mtd->name = "atmel_nand"; in atmel_nand_attach_chip()
1990 } else if (!mtd->name) { in atmel_nand_attach_chip()
1994 * should define the following property in your nand node: in atmel_nand_attach_chip()
1998 * This way, mtd->name will be set by the core when in atmel_nand_attach_chip()
2001 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL, in atmel_nand_attach_chip()
2002 "%s:nand.%d", dev_name(nc->dev), in atmel_nand_attach_chip()
2003 nand->cs[0].id); in atmel_nand_attach_chip()
2004 if (!mtd->name) { in atmel_nand_attach_chip()
2005 dev_err(nc->dev, "Failed to allocate mtd->name\n"); in atmel_nand_attach_chip()
2006 return -ENOMEM; in atmel_nand_attach_chip()
2023 struct device *dev = &pdev->dev; in atmel_nand_controller_init()
2024 struct device_node *np = dev->of_node; in atmel_nand_controller_init()
2027 nand_controller_init(&nc->base); in atmel_nand_controller_init()
2028 nc->base.ops = &atmel_nand_controller_ops; in atmel_nand_controller_init()
2029 INIT_LIST_HEAD(&nc->chips); in atmel_nand_controller_init()
2030 nc->dev = dev; in atmel_nand_controller_init()
2031 nc->caps = caps; in atmel_nand_controller_init()
2035 nc->pmecc = devm_atmel_pmecc_get(dev); in atmel_nand_controller_init()
2036 if (IS_ERR(nc->pmecc)) in atmel_nand_controller_init()
2037 return dev_err_probe(dev, PTR_ERR(nc->pmecc), in atmel_nand_controller_init()
2040 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { in atmel_nand_controller_init()
2046 nc->dmac = dma_request_channel(mask, NULL, NULL); in atmel_nand_controller_init()
2047 if (!nc->dmac) in atmel_nand_controller_init()
2048 dev_err(nc->dev, "Failed to request DMA channel\n"); in atmel_nand_controller_init()
2052 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_init()
2055 nc->mck = of_clk_get(dev->parent->of_node, 0); in atmel_nand_controller_init()
2056 if (IS_ERR(nc->mck)) { in atmel_nand_controller_init()
2058 return PTR_ERR(nc->mck); in atmel_nand_controller_init()
2061 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_nand_controller_init()
2064 return -EINVAL; in atmel_nand_controller_init()
2067 nc->smc = syscon_node_to_regmap(np); in atmel_nand_controller_init()
2069 if (IS_ERR(nc->smc)) { in atmel_nand_controller_init()
2070 ret = PTR_ERR(nc->smc); in atmel_nand_controller_init()
2081 struct device *dev = nc->base.dev; in atmel_smc_nand_controller_init()
2087 if (nc->base.caps->legacy_of_bindings) in atmel_smc_nand_controller_init()
2090 np = of_parse_phandle(dev->parent->of_node, in atmel_smc_nand_controller_init()
2091 nc->base.caps->ebi_csa_regmap_name, 0); in atmel_smc_nand_controller_init()
2101 nc->ebi_csa_regmap = syscon_node_to_regmap(np); in atmel_smc_nand_controller_init()
2103 if (IS_ERR(nc->ebi_csa_regmap)) { in atmel_smc_nand_controller_init()
2104 ret = PTR_ERR(nc->ebi_csa_regmap); in atmel_smc_nand_controller_init()
2109 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; in atmel_smc_nand_controller_init()
2112 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 in atmel_smc_nand_controller_init()
2113 * add 4 to ->ebi_csa->offs. in atmel_smc_nand_controller_init()
2115 if (of_device_is_compatible(dev->parent->of_node, in atmel_smc_nand_controller_init()
2116 "atmel,at91sam9263-ebi1")) in atmel_smc_nand_controller_init()
2117 nc->ebi_csa->offs += 4; in atmel_smc_nand_controller_init()
2131 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_legacy_init()
2137 nand_np = dev->of_node; in atmel_hsmc_nand_controller_legacy_init()
2138 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); in atmel_hsmc_nand_controller_legacy_init()
2140 dev_err(dev, "Could not find device node for sama5d3-nfc\n"); in atmel_hsmc_nand_controller_legacy_init()
2141 return -ENODEV; in atmel_hsmc_nand_controller_legacy_init()
2144 nc->clk = of_clk_get(nfc_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2145 if (IS_ERR(nc->clk)) { in atmel_hsmc_nand_controller_legacy_init()
2146 ret = PTR_ERR(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2152 ret = clk_prepare_enable(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2159 nc->irq = of_irq_get(nand_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2160 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_legacy_init()
2161 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_legacy_init()
2162 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_legacy_init()
2181 regmap_conf.name = "nfc-io"; in atmel_hsmc_nand_controller_legacy_init()
2182 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2183 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2184 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_legacy_init()
2185 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_legacy_init()
2205 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2206 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2207 if (IS_ERR(nc->base.smc)) { in atmel_hsmc_nand_controller_legacy_init()
2208 ret = PTR_ERR(nc->base.smc); in atmel_hsmc_nand_controller_legacy_init()
2221 nc->sram.virt = devm_ioremap_resource(dev, &res); in atmel_hsmc_nand_controller_legacy_init()
2222 if (IS_ERR(nc->sram.virt)) { in atmel_hsmc_nand_controller_legacy_init()
2223 ret = PTR_ERR(nc->sram.virt); in atmel_hsmc_nand_controller_legacy_init()
2227 nc->sram.dma = res.start; in atmel_hsmc_nand_controller_legacy_init()
2238 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_init()
2242 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_hsmc_nand_controller_init()
2245 return -EINVAL; in atmel_hsmc_nand_controller_init()
2248 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); in atmel_hsmc_nand_controller_init()
2250 nc->irq = of_irq_get(np, 0); in atmel_hsmc_nand_controller_init()
2252 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_init()
2253 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_init()
2254 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_init()
2260 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0); in atmel_hsmc_nand_controller_init()
2262 dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); in atmel_hsmc_nand_controller_init()
2263 return -EINVAL; in atmel_hsmc_nand_controller_init()
2266 nc->io = syscon_node_to_regmap(np); in atmel_hsmc_nand_controller_init()
2268 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_init()
2269 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_init()
2274 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, in atmel_hsmc_nand_controller_init()
2275 "atmel,nfc-sram", 0); in atmel_hsmc_nand_controller_init()
2276 if (!nc->sram.pool) { in atmel_hsmc_nand_controller_init()
2277 dev_err(nc->base.dev, "Missing SRAM\n"); in atmel_hsmc_nand_controller_init()
2278 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2281 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool, in atmel_hsmc_nand_controller_init()
2283 &nc->sram.dma); in atmel_hsmc_nand_controller_init()
2284 if (!nc->sram.virt) { in atmel_hsmc_nand_controller_init()
2285 dev_err(nc->base.dev, in atmel_hsmc_nand_controller_init()
2287 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2304 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_remove()
2307 if (hsmc_nc->sram.pool) in atmel_hsmc_nand_controller_remove()
2308 gen_pool_free(hsmc_nc->sram.pool, in atmel_hsmc_nand_controller_remove()
2309 (unsigned long)hsmc_nc->sram.virt, in atmel_hsmc_nand_controller_remove()
2312 if (hsmc_nc->clk) { in atmel_hsmc_nand_controller_remove()
2313 clk_disable_unprepare(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2314 clk_put(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2325 struct device *dev = &pdev->dev; in atmel_hsmc_nand_controller_probe()
2331 return -ENOMEM; in atmel_hsmc_nand_controller_probe()
2333 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_hsmc_nand_controller_probe()
2337 if (caps->legacy_of_bindings) in atmel_hsmc_nand_controller_probe()
2346 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_hsmc_nand_controller_probe()
2347 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt, in atmel_hsmc_nand_controller_probe()
2357 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_controller_probe()
2359 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_probe()
2362 ret = atmel_nand_controller_add_nands(&nc->base); in atmel_hsmc_nand_controller_probe()
2369 atmel_hsmc_nand_controller_remove(&nc->base); in atmel_hsmc_nand_controller_probe()
2402 struct device *dev = &pdev->dev; in atmel_smc_nand_controller_probe()
2408 return -ENOMEM; in atmel_smc_nand_controller_probe()
2410 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_smc_nand_controller_probe()
2418 return atmel_nand_controller_add_nands(&nc->base); in atmel_smc_nand_controller_probe()
2437 * from re-using atmel_smc_nand_setup_interface() for the
2438 * ->setup_interface() hook.
2440 * ->setup_interface() unassigned.
2521 .compatible = "atmel,at91rm9200-nand-controller",
2525 .compatible = "atmel,at91sam9260-nand-controller",
2529 .compatible = "atmel,at91sam9261-nand-controller",
2533 .compatible = "atmel,at91sam9g45-nand-controller",
2537 .compatible = "atmel,sama5d3-nand-controller",
2541 .compatible = "microchip,sam9x60-nand-controller",
2546 .compatible = "atmel,at91rm9200-nand",
2550 .compatible = "atmel,sama5d4-nand",
2554 .compatible = "atmel,sama5d2-nand",
2565 if (pdev->id_entry) in atmel_nand_controller_probe()
2566 caps = (void *)pdev->id_entry->driver_data; in atmel_nand_controller_probe()
2568 caps = of_device_get_match_data(&pdev->dev); in atmel_nand_controller_probe()
2571 dev_err(&pdev->dev, "Could not retrieve NFC caps\n"); in atmel_nand_controller_probe()
2572 return -EINVAL; in atmel_nand_controller_probe()
2575 if (caps->legacy_of_bindings) { in atmel_nand_controller_probe()
2583 nfc_node = of_get_compatible_child(pdev->dev.of_node, in atmel_nand_controller_probe()
2584 "atmel,sama5d3-nfc"); in atmel_nand_controller_probe()
2592 * at91rm9200 controller, the atmel,nand-has-dma specify that in atmel_nand_controller_probe()
2596 if (!caps->has_dma && in atmel_nand_controller_probe()
2597 of_property_read_bool(pdev->dev.of_node, in atmel_nand_controller_probe()
2598 "atmel,nand-has-dma")) in atmel_nand_controller_probe()
2603 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're in atmel_nand_controller_probe()
2606 of_property_read_u32(pdev->dev.of_node, in atmel_nand_controller_probe()
2607 "atmel,nand-addr-offset", &ale_offs); in atmel_nand_controller_probe()
2612 return caps->ops->probe(pdev, caps); in atmel_nand_controller_probe()
2619 return nc->caps->ops->remove(nc); in atmel_nand_controller_remove()
2625 struct atmel_nand *nand; in atmel_nand_controller_resume() local
2627 if (nc->pmecc) in atmel_nand_controller_resume()
2628 atmel_pmecc_reset(nc->pmecc); in atmel_nand_controller_resume()
2630 list_for_each_entry(nand, &nc->chips, node) { in atmel_nand_controller_resume()
2633 for (i = 0; i < nand->numcs; i++) in atmel_nand_controller_resume()
2634 nand_reset(&nand->base, i); in atmel_nand_controller_resume()
2645 .name = "atmel-nand-controller",
2655 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2656 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2657 MODULE_ALIAS("platform:atmel-nand-controller");