Lines Matching +full:nand +full:- +full:no +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
144 * @ecc_conf: Hardware ECC configuration value
145 * @strength: Register value of the ECC strength
148 * @ecc_bits: Exact number of ECC bits per syndrome
149 * @ecc_total: Total number of ECC bytes
174 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
180 * @chips: List of all NAND chips attached to the controller
195 static struct anand *to_anand(struct nand_chip *nand) in to_anand() argument
197 return container_of(nand, struct anand, chip); in to_anand()
210 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val, in anfc_wait_for_event()
214 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event); in anfc_wait_for_event()
215 return -ETIMEDOUT; in anfc_wait_for_event()
218 writel_relaxed(event, nfc->base + INTR_STS_REG); in anfc_wait_for_event()
230 /* There is no R/B interrupt, we must poll a register */ in anfc_wait_for_rb()
231 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val, in anfc_wait_for_rb()
232 val & BIT(anand->rb), in anfc_wait_for_rb()
235 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n", in anfc_wait_for_rb()
236 readl_relaxed(nfc->base + READY_STS_REG)); in anfc_wait_for_rb()
237 return -ETIMEDOUT; in anfc_wait_for_rb()
245 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG); in anfc_trigger_op()
246 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG); in anfc_trigger_op()
247 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG); in anfc_trigger_op()
248 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG); in anfc_trigger_op()
249 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG); in anfc_trigger_op()
264 return -ENOTSUPP; in anfc_pkt_len_config()
276 * When using the embedded hardware ECC engine, the controller is in charge of
277 * feeding the engine with, first, the ECC residue present in the data array.
280 * but targeting the column of the first ECC bytes in the OOB area instead of
282 * 2/ After having read the relevant number of ECC bytes, the controller uses
283 * the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command
286 * will feed the ECC engine with this buffer again.
287 * 4/ The ECC engine derives the ECC bytes for the given data and compare them
293 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
300 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_read_page_hw_ecc()
303 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_read_page_hw_ecc()
309 PKT_SIZE(chip->ecc.size) | in anfc_read_page_hw_ecc()
310 PKT_STEPS(chip->ecc.steps), in anfc_read_page_hw_ecc()
312 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_read_page_hw_ecc()
313 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_read_page_hw_ecc()
316 ADDR2_STRENGTH(anand->strength) | in anfc_read_page_hw_ecc()
317 ADDR2_CS(anand->cs), in anfc_read_page_hw_ecc()
321 CMD_PAGE_SIZE(anand->page_sz) | in anfc_read_page_hw_ecc()
323 CMD_NADDRS(anand->caddr_cycles + in anfc_read_page_hw_ecc()
324 anand->raddr_cycles), in anfc_read_page_hw_ecc()
328 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
329 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_read_page_hw_ecc()
330 dev_err(nfc->dev, "Buffer mapping error"); in anfc_read_page_hw_ecc()
331 return -EIO; in anfc_read_page_hw_ecc()
334 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_read_page_hw_ecc()
335 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_read_page_hw_ecc()
340 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
342 dev_err(nfc->dev, "Error reading page %d\n", page); in anfc_read_page_hw_ecc()
347 ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi, in anfc_read_page_hw_ecc()
348 mtd->oobsize, 0); in anfc_read_page_hw_ecc()
355 * hardware engine feedback. in anfc_read_page_hw_ecc()
357 for (step = 0; step < chip->ecc.steps; step++) { in anfc_read_page_hw_ecc()
358 u8 *raw_buf = &buf[step * chip->ecc.size]; in anfc_read_page_hw_ecc()
363 memset(anand->hw_ecc, 0, chip->ecc.bytes); in anfc_read_page_hw_ecc()
364 nand_extract_bits(anand->hw_ecc, 0, in anfc_read_page_hw_ecc()
365 &chip->oob_poi[mtd->oobsize - anand->ecc_total], in anfc_read_page_hw_ecc()
366 anand->ecc_bits * step, anand->ecc_bits); in anfc_read_page_hw_ecc()
368 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
369 anand->hw_ecc, NULL, NULL, anand->errloc); in anfc_read_page_hw_ecc()
375 if (anand->errloc[i] < (chip->ecc.size * 8)) { in anfc_read_page_hw_ecc()
376 bit = BIT(anand->errloc[i] & 7); in anfc_read_page_hw_ecc()
377 byte = anand->errloc[i] >> 3; in anfc_read_page_hw_ecc()
382 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
388 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
390 chip->ecc.strength); in anfc_read_page_hw_ecc()
392 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
394 memset(raw_buf, 0xFF, chip->ecc.size); in anfc_read_page_hw_ecc()
396 mtd->ecc_stats.failed++; in anfc_read_page_hw_ecc()
407 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_write_page_hw_ecc()
409 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_write_page_hw_ecc()
414 PKT_SIZE(chip->ecc.size) | in anfc_write_page_hw_ecc()
415 PKT_STEPS(chip->ecc.steps), in anfc_write_page_hw_ecc()
417 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_write_page_hw_ecc()
418 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_write_page_hw_ecc()
421 ADDR2_STRENGTH(anand->strength) | in anfc_write_page_hw_ecc()
422 ADDR2_CS(anand->cs), in anfc_write_page_hw_ecc()
426 CMD_PAGE_SIZE(anand->page_sz) | in anfc_write_page_hw_ecc()
428 CMD_NADDRS(anand->caddr_cycles + in anfc_write_page_hw_ecc()
429 anand->raddr_cycles) | in anfc_write_page_hw_ecc()
434 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG); in anfc_write_page_hw_ecc()
436 ECC_SP_ADDRS(anand->caddr_cycles), in anfc_write_page_hw_ecc()
437 nfc->base + ECC_SP_REG); in anfc_write_page_hw_ecc()
439 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
440 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_write_page_hw_ecc()
441 dev_err(nfc->dev, "Buffer mapping error"); in anfc_write_page_hw_ecc()
442 return -EIO; in anfc_write_page_hw_ecc()
445 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_write_page_hw_ecc()
446 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_write_page_hw_ecc()
450 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
452 dev_err(nfc->dev, "Error writing page %d\n", page); in anfc_write_page_hw_ecc()
463 /* NAND framework ->exec_op() hooks and related helpers */
475 nfc_op->addr2_reg = ADDR2_CS(anand->cs); in anfc_parse_instructions()
476 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz); in anfc_parse_instructions()
478 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in anfc_parse_instructions()
483 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
485 switch (instr->type) { in anfc_parse_instructions()
488 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode); in anfc_parse_instructions()
490 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode); in anfc_parse_instructions()
498 addrs = &instr->ctx.addr.addrs[offset]; in anfc_parse_instructions()
499 nfc_op->cmd_reg |= CMD_NADDRS(naddrs); in anfc_parse_instructions()
503 nfc_op->addr1_reg |= (u32)addrs[i] << i * 8; in anfc_parse_instructions()
505 nfc_op->addr2_reg |= addrs[i]; in anfc_parse_instructions()
510 nfc_op->read = true; in anfc_parse_instructions()
514 buf = instr->ctx.data.buf.in; in anfc_parse_instructions()
515 nfc_op->buf = &buf[offset]; in anfc_parse_instructions()
516 nfc_op->len = nand_subop_get_data_len(subop, op_id); in anfc_parse_instructions()
517 ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps, in anfc_parse_instructions()
536 nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) | in anfc_parse_instructions()
537 PKT_STEPS(nfc_op->steps); in anfc_parse_instructions()
540 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in anfc_parse_instructions()
550 unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps; in anfc_rw_pio_op()
551 unsigned int last_len = nfc_op->len % 4; in anfc_rw_pio_op()
553 u8 *buf = nfc_op->buf; in anfc_rw_pio_op()
556 for (i = 0; i < nfc_op->steps; i++) { in anfc_rw_pio_op()
557 dir = nfc_op->read ? READ_READY : WRITE_READY; in anfc_rw_pio_op()
560 dev_err(nfc->dev, "PIO %s ready signal not received\n", in anfc_rw_pio_op()
561 nfc_op->read ? "Read" : "Write"); in anfc_rw_pio_op()
566 if (nfc_op->read) in anfc_rw_pio_op()
567 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
570 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
577 offset = nfc_op->len - last_len; in anfc_rw_pio_op()
579 if (nfc_op->read) { in anfc_rw_pio_op()
580 remainder = readl_relaxed(nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
584 writel_relaxed(remainder, nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
595 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_data_type_exec()
643 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_zerolen_type_exec()
667 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_status_type_exec()
672 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) in anfc_status_type_exec()
673 return -ENOTSUPP; in anfc_status_type_exec()
679 tmp = readl_relaxed(nfc->base + FLASH_STS_REG); in anfc_status_type_exec()
680 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); in anfc_status_type_exec()
700 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_wait_type_exec()
758 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_select_target()
761 /* Update the controller timings and the potential ECC configuration */ in anfc_select_target()
762 writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); in anfc_select_target()
765 if (nfc->cur_clk != anand->clk) { in anfc_select_target()
766 clk_disable_unprepare(nfc->controller_clk); in anfc_select_target()
767 ret = clk_set_rate(nfc->controller_clk, anand->clk); in anfc_select_target()
769 dev_err(nfc->dev, "Failed to change clock rate\n"); in anfc_select_target()
773 ret = clk_prepare_enable(nfc->controller_clk); in anfc_select_target()
775 dev_err(nfc->dev, in anfc_select_target()
776 "Failed to re-enable the controller clock\n"); in anfc_select_target()
780 nfc->cur_clk = anand->clk; in anfc_select_target()
793 * The controller abstracts all the NAND operations and do not support in anfc_check_op()
799 for (op_id = 0; op_id < op->ninstrs; op_id++) { in anfc_check_op()
800 instr = &op->instrs[op_id]; in anfc_check_op()
802 switch (instr->type) { in anfc_check_op()
804 if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC) in anfc_check_op()
805 return -ENOTSUPP; in anfc_check_op()
810 if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE) in anfc_check_op()
811 return -ENOTSUPP; in anfc_check_op()
813 if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0)) in anfc_check_op()
814 return -ENOTSUPP; in anfc_check_op()
830 * fixed patterns instead of open-coding this check here. in anfc_check_op()
832 if (op->ninstrs == 2 && in anfc_check_op()
833 op->instrs[0].type == NAND_OP_CMD_INSTR && in anfc_check_op()
834 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && in anfc_check_op()
835 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in anfc_check_op()
836 return -ENOTSUPP; in anfc_check_op()
850 ret = anfc_select_target(chip, op->cs); in anfc_exec_op()
861 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_setup_interface()
862 struct device_node *np = nfc->dev->of_node; in anfc_setup_interface()
867 anand->timings = DIFACE_SDR | DIFACE_SDR_MODE(conf->timings.mode); in anfc_setup_interface()
868 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; in anfc_setup_interface()
871 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work in anfc_setup_interface()
874 * 80MHz when using modes 2-5 with this SoC. in anfc_setup_interface()
876 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") && in anfc_setup_interface()
877 conf->timings.mode >= 2) in anfc_setup_interface()
878 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK; in anfc_setup_interface()
895 return -EINVAL; in anfc_calc_hw_ecc_bytes()
931 struct nand_ecc_ctrl *ecc = &chip->ecc; in anfc_init_hw_ecc_controller() local
935 switch (mtd->writesize) { in anfc_init_hw_ecc_controller()
943 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize); in anfc_init_hw_ecc_controller()
944 return -EINVAL; in anfc_init_hw_ecc_controller()
947 ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize); in anfc_init_hw_ecc_controller()
951 switch (ecc->strength) { in anfc_init_hw_ecc_controller()
953 anand->strength = 0x1; in anfc_init_hw_ecc_controller()
956 anand->strength = 0x2; in anfc_init_hw_ecc_controller()
959 anand->strength = 0x3; in anfc_init_hw_ecc_controller()
962 anand->strength = 0x4; in anfc_init_hw_ecc_controller()
965 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
966 return -EINVAL; in anfc_init_hw_ecc_controller()
969 switch (ecc->size) { in anfc_init_hw_ecc_controller()
979 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
980 return -EINVAL; in anfc_init_hw_ecc_controller()
985 ecc->steps = mtd->writesize / ecc->size; in anfc_init_hw_ecc_controller()
986 ecc->algo = NAND_ECC_ALGO_BCH; in anfc_init_hw_ecc_controller()
987 anand->ecc_bits = bch_gf_mag * ecc->strength; in anfc_init_hw_ecc_controller()
988 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8); in anfc_init_hw_ecc_controller()
989 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8); in anfc_init_hw_ecc_controller()
990 ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total; in anfc_init_hw_ecc_controller()
991 anand->ecc_conf = ECC_CONF_COL(ecc_offset) | in anfc_init_hw_ecc_controller()
992 ECC_CONF_LEN(anand->ecc_total) | in anfc_init_hw_ecc_controller()
995 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength, in anfc_init_hw_ecc_controller()
996 sizeof(*anand->errloc), GFP_KERNEL); in anfc_init_hw_ecc_controller()
997 if (!anand->errloc) in anfc_init_hw_ecc_controller()
998 return -ENOMEM; in anfc_init_hw_ecc_controller()
1000 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL); in anfc_init_hw_ecc_controller()
1001 if (!anand->hw_ecc) in anfc_init_hw_ecc_controller()
1002 return -ENOMEM; in anfc_init_hw_ecc_controller()
1005 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); in anfc_init_hw_ecc_controller()
1006 if (!anand->bch) in anfc_init_hw_ecc_controller()
1007 return -EINVAL; in anfc_init_hw_ecc_controller()
1009 ecc->read_page = anfc_read_page_hw_ecc; in anfc_init_hw_ecc_controller()
1010 ecc->write_page = anfc_write_page_hw_ecc; in anfc_init_hw_ecc_controller()
1018 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_attach_chip()
1022 if (mtd->writesize <= SZ_512) in anfc_attach_chip()
1023 anand->caddr_cycles = 1; in anfc_attach_chip()
1025 anand->caddr_cycles = 2; in anfc_attach_chip()
1027 if (chip->options & NAND_ROW_ADDR_3) in anfc_attach_chip()
1028 anand->raddr_cycles = 3; in anfc_attach_chip()
1030 anand->raddr_cycles = 2; in anfc_attach_chip()
1032 switch (mtd->writesize) { in anfc_attach_chip()
1034 anand->page_sz = 0; in anfc_attach_chip()
1037 anand->page_sz = 5; in anfc_attach_chip()
1040 anand->page_sz = 1; in anfc_attach_chip()
1043 anand->page_sz = 2; in anfc_attach_chip()
1046 anand->page_sz = 3; in anfc_attach_chip()
1049 anand->page_sz = 4; in anfc_attach_chip()
1052 return -EINVAL; in anfc_attach_chip()
1055 /* These hooks are valid for all ECC providers */ in anfc_attach_chip()
1056 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; in anfc_attach_chip()
1057 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; in anfc_attach_chip()
1059 switch (chip->ecc.engine_type) { in anfc_attach_chip()
1068 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", in anfc_attach_chip()
1069 chip->ecc.engine_type); in anfc_attach_chip()
1070 return -EINVAL; in anfc_attach_chip()
1080 if (anand->bch) in anfc_detach_chip()
1081 bch_free(anand->bch); in anfc_detach_chip()
1098 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL); in anfc_chip_init()
1100 return -ENOMEM; in anfc_chip_init()
1104 dev_err(nfc->dev, "Invalid reg property\n"); in anfc_chip_init()
1105 return -EINVAL; in anfc_chip_init()
1112 ret = of_property_read_u32(np, "nand-rb", &rb); in anfc_chip_init()
1117 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb); in anfc_chip_init()
1118 return -EINVAL; in anfc_chip_init()
1121 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in anfc_chip_init()
1122 dev_err(nfc->dev, "Already assigned CS %d\n", cs); in anfc_chip_init()
1123 return -EINVAL; in anfc_chip_init()
1126 anand->cs = cs; in anfc_chip_init()
1127 anand->rb = rb; in anfc_chip_init()
1129 chip = &anand->chip; in anfc_chip_init()
1131 mtd->dev.parent = nfc->dev; in anfc_chip_init()
1132 chip->controller = &nfc->controller; in anfc_chip_init()
1133 chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | in anfc_chip_init()
1137 if (!mtd->name) { in anfc_chip_init()
1138 dev_err(nfc->dev, "NAND label property is mandatory\n"); in anfc_chip_init()
1139 return -EINVAL; in anfc_chip_init()
1144 dev_err(nfc->dev, "Scan operation failed\n"); in anfc_chip_init()
1154 list_add_tail(&anand->node, &nfc->chips); in anfc_chip_init()
1165 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) { in anfc_chips_cleanup()
1166 chip = &anand->chip; in anfc_chips_cleanup()
1170 list_del(&anand->node); in anfc_chips_cleanup()
1176 struct device_node *np = nfc->dev->of_node, *nand_np; in anfc_chips_init()
1181 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n", in anfc_chips_init()
1183 return -EINVAL; in anfc_chips_init()
1201 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG); in anfc_reset()
1204 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG); in anfc_reset()
1212 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); in anfc_probe()
1214 return -ENOMEM; in anfc_probe()
1216 nfc->dev = &pdev->dev; in anfc_probe()
1217 nand_controller_init(&nfc->controller); in anfc_probe()
1218 nfc->controller.ops = &anfc_ops; in anfc_probe()
1219 INIT_LIST_HEAD(&nfc->chips); in anfc_probe()
1221 nfc->base = devm_platform_ioremap_resource(pdev, 0); in anfc_probe()
1222 if (IS_ERR(nfc->base)) in anfc_probe()
1223 return PTR_ERR(nfc->base); in anfc_probe()
1227 nfc->controller_clk = devm_clk_get(&pdev->dev, "controller"); in anfc_probe()
1228 if (IS_ERR(nfc->controller_clk)) in anfc_probe()
1229 return PTR_ERR(nfc->controller_clk); in anfc_probe()
1231 nfc->bus_clk = devm_clk_get(&pdev->dev, "bus"); in anfc_probe()
1232 if (IS_ERR(nfc->bus_clk)) in anfc_probe()
1233 return PTR_ERR(nfc->bus_clk); in anfc_probe()
1235 ret = clk_prepare_enable(nfc->controller_clk); in anfc_probe()
1239 ret = clk_prepare_enable(nfc->bus_clk); in anfc_probe()
1252 clk_disable_unprepare(nfc->bus_clk); in anfc_probe()
1255 clk_disable_unprepare(nfc->controller_clk); in anfc_probe()
1266 clk_disable_unprepare(nfc->bus_clk); in anfc_remove()
1267 clk_disable_unprepare(nfc->controller_clk); in anfc_remove()
1274 .compatible = "xlnx,zynqmp-nand-controller",
1277 .compatible = "arasan,nfc-v3p10",
1285 .name = "arasan-nand-controller",
1297 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");