Lines Matching +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
233 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
242 /* 4C-4F reserved for more max current */
249 /* 55-57 reserved */
254 /* 60-FB reserved */
261 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
291 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
293 /* ADMA2 32-bit DMA descriptor size */
296 /* ADMA2 32-bit descriptor */
305 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
309 * alignment for the descriptor table even in 32-bit DMA mode. Memory
315 * ADMA2 64-bit DMA descriptor size
317 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
319 * register, 128-bit Descriptor will be selected.
321 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
324 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
348 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
365 unsigned int quirks; /* Deviations from spec. */
367 /* Controller doesn't honor resets unless we touch the clock register */
381 /* Controller can only DMA from 32-bit aligned addresses */
387 /* Controller needs to be reset after each request to stay stable */
395 /* Controller does not provide transfer-complete interrupt when not busy */
399 /* Controller reports inverted write-protect state */
409 /* Controller cannot do multi-block transfers */
411 /* Controller can only handle 1-bit data transfers */
413 /* Controller needs 10ms delay between applying power and clock */
417 /* Controller reports wrong base clock capability */
425 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
429 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
432 unsigned int quirks2; /* More deviations from spec. */
440 /* Controller has a non-standard host control register */
448 /* Controller does not support 64-bit DMA */
452 /* Capability register bit-63 indicates HS400 support */
454 /* forced tuned clock */
458 /* Controller broken with using ACMD23 */
460 /* Broken Clock divider zero in controller */
470 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
471 * for other purposes. Consequently we support 16-bit block count by default.
472 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
477 int irq; /* Device IRQ */
482 unsigned int bounce_buffer_size;
498 int flags; /* Host attributes */
507 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
513 unsigned int version; /* SDHCI spec. version */
515 unsigned int max_clk; /* Max possible freq (MHz) */
516 unsigned int timeout_clk; /* Timeout freq (KHz) */
517 unsigned int clk_mul; /* Clock Muliplier value */
519 unsigned int clock; /* Current clock (MHz) */ member
536 unsigned int data_early:1; /* Data finished before cmd */
539 unsigned int blocks; /* remaining PIO blocks */
541 int sg_count; /* Mapped sg entries */
552 unsigned int desc_sz; /* ADMA current descriptor size */
553 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
571 unsigned int ocr_avail_sdio; /* OCR bit masks */
572 unsigned int ocr_avail_sd;
573 unsigned int ocr_avail_mmc;
588 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
590 unsigned int tuning_count; /* Timer count for re-tuning */
591 unsigned int tuning_mode; /* Re-tuning mode supported by host */
592 unsigned int tuning_err; /* Error code for re-tuning */
597 int tuning_delay;
598 int tuning_loop_count;
613 u32 (*read_l)(struct sdhci_host *host, int reg);
614 u16 (*read_w)(struct sdhci_host *host, int reg);
615 u8 (*read_b)(struct sdhci_host *host, int reg);
616 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
617 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
618 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
621 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
627 int (*set_dma_mask)(struct sdhci_host *host);
628 int (*enable_dma)(struct sdhci_host *host);
629 unsigned int (*get_max_clock)(struct sdhci_host *host);
630 unsigned int (*get_min_clock)(struct sdhci_host *host);
632 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
633 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
636 void (*set_bus_width)(struct sdhci_host *host, int width);
639 unsigned int (*get_ro)(struct sdhci_host *host);
641 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
642 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
648 dma_addr_t addr, int len, unsigned int cmd);
651 unsigned int length);
659 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
661 if (unlikely(host->ops->write_l)) in sdhci_writel()
662 host->ops->write_l(host, val, reg); in sdhci_writel()
664 writel(val, host->ioaddr + reg); in sdhci_writel()
667 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
669 if (unlikely(host->ops->write_w)) in sdhci_writew()
670 host->ops->write_w(host, val, reg); in sdhci_writew()
672 writew(val, host->ioaddr + reg); in sdhci_writew()
675 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
677 if (unlikely(host->ops->write_b)) in sdhci_writeb()
678 host->ops->write_b(host, val, reg); in sdhci_writeb()
680 writeb(val, host->ioaddr + reg); in sdhci_writeb()
683 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
685 if (unlikely(host->ops->read_l)) in sdhci_readl()
686 return host->ops->read_l(host, reg); in sdhci_readl()
688 return readl(host->ioaddr + reg); in sdhci_readl()
691 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
693 if (unlikely(host->ops->read_w)) in sdhci_readw()
694 return host->ops->read_w(host, reg); in sdhci_readw()
696 return readw(host->ioaddr + reg); in sdhci_readw()
699 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
701 if (unlikely(host->ops->read_b)) in sdhci_readb()
702 return host->ops->read_b(host, reg); in sdhci_readb()
704 return readb(host->ioaddr + reg); in sdhci_readb()
709 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
711 writel(val, host->ioaddr + reg); in sdhci_writel()
714 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
716 writew(val, host->ioaddr + reg); in sdhci_writew()
719 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
721 writeb(val, host->ioaddr + reg); in sdhci_writeb()
724 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
726 return readl(host->ioaddr + reg); in sdhci_readl()
729 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
731 return readw(host->ioaddr + reg); in sdhci_readw()
734 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
736 return readb(host->ioaddr + reg); in sdhci_readb()
746 return host->private; in sdhci_priv()
752 int sdhci_setup_host(struct sdhci_host *host);
754 int __sdhci_add_host(struct sdhci_host *host);
755 int sdhci_add_host(struct sdhci_host *host);
756 void sdhci_remove_host(struct sdhci_host *host, int dead);
763 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
764 unsigned int *actual_clock);
765 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
775 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
776 void sdhci_set_bus_width(struct sdhci_host *host, int width);
779 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
781 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
783 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
785 dma_addr_t addr, int len, unsigned int cmd);
788 int sdhci_suspend_host(struct sdhci_host *host);
789 int sdhci_resume_host(struct sdhci_host *host);
790 int sdhci_runtime_suspend_host(struct sdhci_host *host);
791 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
796 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
797 int *data_error);