1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
166 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
188 #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
233 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
242 /* 4C-4F reserved for more max current */
249 /* 55-57 reserved */
254 /* 60-FB reserved */
261 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
291 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
293 /* ADMA2 32-bit DMA descriptor size */
296 /* ADMA2 32-bit descriptor */
305 #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
309  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
315  * ADMA2 64-bit DMA descriptor size
317  * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
319  * register, 128-bit Descriptor will be selected.
321 #define SDHCI_ADMA2_64_DESC_SZ(host)	((host)->v4_mode ? 16 : 12)
324  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
381 /* Controller can only DMA from 32-bit aligned addresses */
395 /* Controller does not provide transfer-complete interrupt when not busy */
399 /* Controller reports inverted write-protect state */
409 /* Controller cannot do multi-block transfers */
411 /* Controller can only handle 1-bit data transfers */
423 /* Controller uses Auto CMD12 command to stop the transfer */
425 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
429 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
440 /* Controller has a non-standard host control register */
446 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
448 /* Controller does not support 64-bit DMA */
452 /* Capability register bit-63 indicates HS400 support */
470  * 32-bit block count may not support eMMC where upper bits of CMD23 are used
471  * for other purposes.  Consequently we support 16-bit block count by default.
472  * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
504 #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
505 #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
507 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
590 	unsigned int		tuning_count;	/* Timer count for re-tuning */
591 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
592 	unsigned int		tuning_err;	/* Error code for re-tuning */
661 	if (unlikely(host->ops->write_l))  in sdhci_writel()
662 		host->ops->write_l(host, val, reg);  in sdhci_writel()
664 		writel(val, host->ioaddr + reg);  in sdhci_writel()
669 	if (unlikely(host->ops->write_w))  in sdhci_writew()
670 		host->ops->write_w(host, val, reg);  in sdhci_writew()
672 		writew(val, host->ioaddr + reg);  in sdhci_writew()
677 	if (unlikely(host->ops->write_b))  in sdhci_writeb()
678 		host->ops->write_b(host, val, reg);  in sdhci_writeb()
680 		writeb(val, host->ioaddr + reg);  in sdhci_writeb()
685 	if (unlikely(host->ops->read_l))  in sdhci_readl()
686 		return host->ops->read_l(host, reg);  in sdhci_readl()
688 		return readl(host->ioaddr + reg);  in sdhci_readl()
693 	if (unlikely(host->ops->read_w))  in sdhci_readw()
694 		return host->ops->read_w(host, reg);  in sdhci_readw()
696 		return readw(host->ioaddr + reg);  in sdhci_readw()
701 	if (unlikely(host->ops->read_b))  in sdhci_readb()
702 		return host->ops->read_b(host, reg);  in sdhci_readb()
704 		return readb(host->ioaddr + reg);  in sdhci_readb()
711 	writel(val, host->ioaddr + reg);  in sdhci_writel()
716 	writew(val, host->ioaddr + reg);  in sdhci_writew()
721 	writeb(val, host->ioaddr + reg);  in sdhci_writeb()
726 	return readl(host->ioaddr + reg);  in sdhci_readl()
731 	return readw(host->ioaddr + reg);  in sdhci_readw()
736 	return readb(host->ioaddr + reg);  in sdhci_readb()
746 	return host->private;  in sdhci_priv()