125 	u32 nvquirks;  member
178 	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&  in tegra_sdhci_readw()
223 	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&  in tegra_sdhci_writel()
304 	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))  in tegra_sdhci_is_pad_and_regulator_valid()
337 	if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)  in tegra_sdhci_set_tap()
345 	if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&  in tegra_sdhci_set_tap()
397 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)  in tegra_sdhci_reset()
400 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)  in tegra_sdhci_reset()
402 		if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)  in tegra_sdhci_reset()
404 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)  in tegra_sdhci_reset()
406 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)  in tegra_sdhci_reset()
415 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {  in tegra_sdhci_reset()
653 	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))  in tegra_sdhci_parse_pad_autocal_dt()
1152 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)  in tegra_sdhci_voltage_switch()
1200 	if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&  in sdhci_tegra_update_dcmd_desc()
1331 	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1358 	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1439 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1477 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1491 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1587 	if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {  in sdhci_tegra_probe()
1595 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)  in sdhci_tegra_probe()
1609 	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)  in sdhci_tegra_probe()
1639 	if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {  in sdhci_tegra_probe()