154 	u32 scratch_32;  in o2_pci_set_baseclk()  local
157 			      O2_SD_PLL_SETTING, &scratch_32);  in o2_pci_set_baseclk()
159 	scratch_32 &= 0x0000FFFF;  in o2_pci_set_baseclk()
160 	scratch_32 |= value;  in o2_pci_set_baseclk()
163 			       O2_SD_PLL_SETTING, scratch_32);  in o2_pci_set_baseclk()
233 	u32 scratch_32 = 0;  in sdhci_o2_dll_recovery()  local
248 		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
249 		scratch_32 |= O2_PLL_SOFT_RESET;  in sdhci_o2_dll_recovery()
250 		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
254 					    &scratch_32);  in sdhci_o2_dll_recovery()
256 		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_o2_dll_recovery()
257 		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);  in sdhci_o2_dll_recovery()
357 	u32 scratch_32;  in o2_pci_led_enable()  local
361 				    O2_SD_FUNC_REG0, &scratch_32);  in o2_pci_led_enable()
365 	scratch_32 &= ~O2_SD_FREG0_LEDOFF;  in o2_pci_led_enable()
367 			       O2_SD_FUNC_REG0, scratch_32);  in o2_pci_led_enable()
370 				    O2_SD_TEST_REG, &scratch_32);  in o2_pci_led_enable()
374 	scratch_32 |= O2_SD_LED_ENABLE;  in o2_pci_led_enable()
376 			       O2_SD_TEST_REG, scratch_32);  in o2_pci_led_enable()
381 	u32 scratch_32;  in sdhci_pci_o2_fujin2_pci_init()  local
384 	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
387 	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));  in sdhci_pci_o2_fujin2_pci_init()
388 	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
391 	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
394 	scratch_32 &= ~((1 << 19) | (1 << 11));  in sdhci_pci_o2_fujin2_pci_init()
395 	scratch_32 |= (1 << 10);  in sdhci_pci_o2_fujin2_pci_init()
396 	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
399 	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
402 	scratch_32 |= (1 << 4);  in sdhci_pci_o2_fujin2_pci_init()
403 	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
409 	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
412 	scratch_32 &= ~(3 << 12);  in sdhci_pci_o2_fujin2_pci_init()
413 	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
416 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
419 	scratch_32 &= ~(0x01FE);  in sdhci_pci_o2_fujin2_pci_init()
420 	scratch_32 |= 0x00CC;  in sdhci_pci_o2_fujin2_pci_init()
421 	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
424 				    O2_SD_TUNING_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
427 	scratch_32 &= ~(0x000000FF);  in sdhci_pci_o2_fujin2_pci_init()
428 	scratch_32 |= 0x00000066;  in sdhci_pci_o2_fujin2_pci_init()
429 	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
433 				    O2_SD_UHS2_L1_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
436 	scratch_32 &= ~(0x000000FC);  in sdhci_pci_o2_fujin2_pci_init()
437 	scratch_32 |= 0x00000084;  in sdhci_pci_o2_fujin2_pci_init()
438 	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
441 	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
444 	scratch_32 &= ~((1 << 21) | (1 << 30));  in sdhci_pci_o2_fujin2_pci_init()
446 	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
449 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
452 	scratch_32 &= ~(0xf0000000);  in sdhci_pci_o2_fujin2_pci_init()
453 	scratch_32 |= 0x30000000;  in sdhci_pci_o2_fujin2_pci_init()
454 	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
457 				    O2_SD_MISC_CTRL4, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
460 	scratch_32 &= ~(0x000f0000);  in sdhci_pci_o2_fujin2_pci_init()
461 	scratch_32 |= 0x00080000;  in sdhci_pci_o2_fujin2_pci_init()
462 	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
505 	u32 scratch_32;  in sdhci_pci_o2_set_clock()  local
522 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
524 		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)  in sdhci_pci_o2_set_clock()
616 	u32 scratch_32;  in sdhci_pci_o2_probe()  local
688 						    &scratch_32);  in sdhci_pci_o2_probe()
689 			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);  in sdhci_pci_o2_probe()
692 			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {  in sdhci_pci_o2_probe()
693 				scratch_32 = 0x25100000;  in sdhci_pci_o2_probe()
695 				o2_pci_set_baseclk(chip, scratch_32);  in sdhci_pci_o2_probe()
698 							    &scratch_32);  in sdhci_pci_o2_probe()
701 				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_pci_o2_probe()
704 						       scratch_32);  in sdhci_pci_o2_probe()
719 					    O2_SD_CLK_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
723 		scratch_32 &= ~(0xFF00);  in sdhci_pci_o2_probe()
724 		scratch_32 |= 0x07E0C800;  in sdhci_pci_o2_probe()
726 				       O2_SD_CLK_SETTING, scratch_32);  in sdhci_pci_o2_probe()
729 					    O2_SD_CLKREQ, &scratch_32);  in sdhci_pci_o2_probe()
732 		scratch_32 |= 0x3;  in sdhci_pci_o2_probe()
733 		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);  in sdhci_pci_o2_probe()
736 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
740 		scratch_32 &= ~(0x1F3F070E);  in sdhci_pci_o2_probe()
741 		scratch_32 |= 0x18270106;  in sdhci_pci_o2_probe()
743 				       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
747 					    O2_SD_CAP_REG2, &scratch_32);  in sdhci_pci_o2_probe()
750 		scratch_32 &= ~(0xE0);  in sdhci_pci_o2_probe()
752 				       O2_SD_CAP_REG2, scratch_32);  in sdhci_pci_o2_probe()
777 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
779 		if ((scratch_32 & 0xff000000) == 0x01000000) {  in sdhci_pci_o2_probe()
780 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
781 			scratch_32 |= 0x1F340000;  in sdhci_pci_o2_probe()
784 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
786 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
787 			scratch_32 |= 0x25100000;  in sdhci_pci_o2_probe()
790 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
794 						    &scratch_32);  in sdhci_pci_o2_probe()
795 			scratch_32 |= (1 << 22);  in sdhci_pci_o2_probe()
797 					       O2_SD_FUNC_REG4, scratch_32);  in sdhci_pci_o2_probe()