Lines Matching +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken
1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/mmc/slot-gpio.h>
23 #include "sdhci-pltfm.h"
35 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
40 unsigned int divider_for_baseclk;
56 mc1r = readb(host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
58 writeb(mc1r, host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
61 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_at91_set_clock() argument
66 host->mmc->actual_clock = 0; in sdhci_at91_set_clock()
69 * There is no requirement to disable the internal clock before in sdhci_at91_set_clock()
70 * changing the SD clock configuration. Moreover, disabling the in sdhci_at91_set_clock()
71 * internal clock, changing the configuration and re-enabling the in sdhci_at91_set_clock()
72 * internal clock causes some bugs. It can prevent to get the internal in sdhci_at91_set_clock()
73 * clock stable flag ready and an unexpected switch to the base clock in sdhci_at91_set_clock()
80 if (clock == 0) in sdhci_at91_set_clock()
83 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_at91_set_clock()
93 pr_err("%s: Internal clock never stabilised.\n", in sdhci_at91_set_clock()
94 mmc_hostname(host->mmc)); in sdhci_at91_set_clock()
97 timeout--; in sdhci_at91_set_clock()
106 unsigned int timing) in sdhci_at91_set_uhs_signaling()
120 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_at91_reset()
121 || mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_at91_reset()
124 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) { in sdhci_at91_reset()
156 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
157 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
162 static int sdhci_at91_set_clks_presets(struct device *dev) in sdhci_at91_set_clks_presets()
167 unsigned int caps0, caps1; in sdhci_at91_set_clks_presets()
168 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets()
169 unsigned int gck_rate, clk_base_rate; in sdhci_at91_set_clks_presets()
170 unsigned int preset_div; in sdhci_at91_set_clks_presets()
172 clk_prepare_enable(priv->hclock); in sdhci_at91_set_clks_presets()
173 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_at91_set_clks_presets()
174 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); in sdhci_at91_set_clks_presets()
176 gck_rate = clk_get_rate(priv->gck); in sdhci_at91_set_clks_presets()
177 if (priv->soc_data->baseclk_is_generated_internally) in sdhci_at91_set_clks_presets()
178 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; in sdhci_at91_set_clks_presets()
180 clk_base_rate = clk_get_rate(priv->mainck); in sdhci_at91_set_clks_presets()
183 clk_mul = gck_rate / clk_base_rate - 1; in sdhci_at91_set_clks_presets()
190 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); in sdhci_at91_set_clks_presets()
191 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); in sdhci_at91_set_clks_presets()
192 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); in sdhci_at91_set_clks_presets()
194 writel(0, host->ioaddr + SDMMC_CACR); in sdhci_at91_set_clks_presets()
202 * maximum sd clock value is 120 MHz instead of 208 MHz. For that in sdhci_at91_set_clks_presets()
205 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; in sdhci_at91_set_clks_presets()
207 host->ioaddr + SDHCI_PRESET_FOR_SDR12); in sdhci_at91_set_clks_presets()
208 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; in sdhci_at91_set_clks_presets()
210 host->ioaddr + SDHCI_PRESET_FOR_SDR25); in sdhci_at91_set_clks_presets()
211 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; in sdhci_at91_set_clks_presets()
213 host->ioaddr + SDHCI_PRESET_FOR_SDR50); in sdhci_at91_set_clks_presets()
214 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; in sdhci_at91_set_clks_presets()
216 host->ioaddr + SDHCI_PRESET_FOR_SDR104); in sdhci_at91_set_clks_presets()
217 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; in sdhci_at91_set_clks_presets()
219 host->ioaddr + SDHCI_PRESET_FOR_DDR50); in sdhci_at91_set_clks_presets()
221 clk_prepare_enable(priv->mainck); in sdhci_at91_set_clks_presets()
222 clk_prepare_enable(priv->gck); in sdhci_at91_set_clks_presets()
228 static int sdhci_at91_suspend(struct device *dev) in sdhci_at91_suspend()
233 int ret; in sdhci_at91_suspend()
237 priv->restore_needed = true; in sdhci_at91_suspend()
244 static int sdhci_at91_runtime_suspend(struct device *dev) in sdhci_at91_runtime_suspend()
249 int ret; in sdhci_at91_runtime_suspend()
253 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_at91_runtime_suspend()
254 mmc_retune_needed(host->mmc); in sdhci_at91_runtime_suspend()
256 clk_disable_unprepare(priv->gck); in sdhci_at91_runtime_suspend()
257 clk_disable_unprepare(priv->hclock); in sdhci_at91_runtime_suspend()
258 clk_disable_unprepare(priv->mainck); in sdhci_at91_runtime_suspend()
263 static int sdhci_at91_runtime_resume(struct device *dev) in sdhci_at91_runtime_resume()
268 int ret; in sdhci_at91_runtime_resume()
270 if (priv->restore_needed) { in sdhci_at91_runtime_resume()
275 priv->restore_needed = false; in sdhci_at91_runtime_resume()
279 ret = clk_prepare_enable(priv->mainck); in sdhci_at91_runtime_resume()
285 ret = clk_prepare_enable(priv->hclock); in sdhci_at91_runtime_resume()
291 ret = clk_prepare_enable(priv->gck); in sdhci_at91_runtime_resume()
309 static int sdhci_at91_probe(struct platform_device *pdev) in sdhci_at91_probe()
316 int ret; in sdhci_at91_probe()
318 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); in sdhci_at91_probe()
320 return -EINVAL; in sdhci_at91_probe()
321 soc_data = match->data; in sdhci_at91_probe()
323 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); in sdhci_at91_probe()
329 priv->soc_data = soc_data; in sdhci_at91_probe()
331 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); in sdhci_at91_probe()
332 if (IS_ERR(priv->mainck)) { in sdhci_at91_probe()
333 if (soc_data->baseclk_is_generated_internally) { in sdhci_at91_probe()
334 priv->mainck = NULL; in sdhci_at91_probe()
336 dev_err(&pdev->dev, "failed to get baseclk\n"); in sdhci_at91_probe()
337 ret = PTR_ERR(priv->mainck); in sdhci_at91_probe()
342 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); in sdhci_at91_probe()
343 if (IS_ERR(priv->hclock)) { in sdhci_at91_probe()
344 dev_err(&pdev->dev, "failed to get hclock\n"); in sdhci_at91_probe()
345 ret = PTR_ERR(priv->hclock); in sdhci_at91_probe()
349 priv->gck = devm_clk_get(&pdev->dev, "multclk"); in sdhci_at91_probe()
350 if (IS_ERR(priv->gck)) { in sdhci_at91_probe()
351 dev_err(&pdev->dev, "failed to get multclk\n"); in sdhci_at91_probe()
352 ret = PTR_ERR(priv->gck); in sdhci_at91_probe()
356 ret = sdhci_at91_set_clks_presets(&pdev->dev); in sdhci_at91_probe()
360 priv->restore_needed = false; in sdhci_at91_probe()
366 priv->cal_always_on = in sdhci_at91_probe()
367 device_property_read_bool(&pdev->dev, in sdhci_at91_probe()
368 "microchip,sdcal-inverted"); in sdhci_at91_probe()
370 ret = mmc_of_parse(host->mmc); in sdhci_at91_probe()
376 pm_runtime_get_noresume(&pdev->dev); in sdhci_at91_probe()
377 pm_runtime_set_active(&pdev->dev); in sdhci_at91_probe()
378 pm_runtime_enable(&pdev->dev); in sdhci_at91_probe()
379 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_at91_probe()
380 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_at91_probe()
382 /* HS200 is broken at this moment */ in sdhci_at91_probe()
383 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_at91_probe()
393 * For that reason, it is not planned to wake-up on a card detect irq in sdhci_at91_probe()
395 * If we want to use runtime PM and to be able to wake-up on card in sdhci_at91_probe()
400 * to enable polling via device tree with broken-cd property. in sdhci_at91_probe()
402 if (mmc_card_is_removable(host->mmc) && in sdhci_at91_probe()
403 mmc_gpio_get_cd(host->mmc) < 0) { in sdhci_at91_probe()
404 host->mmc->caps |= MMC_CAP_NEEDS_POLL; in sdhci_at91_probe()
405 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_at91_probe()
422 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_at91_probe()
423 || mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_at91_probe()
426 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_at91_probe()
431 pm_runtime_disable(&pdev->dev); in sdhci_at91_probe()
432 pm_runtime_set_suspended(&pdev->dev); in sdhci_at91_probe()
433 pm_runtime_put_noidle(&pdev->dev); in sdhci_at91_probe()
435 clk_disable_unprepare(priv->gck); in sdhci_at91_probe()
436 clk_disable_unprepare(priv->mainck); in sdhci_at91_probe()
437 clk_disable_unprepare(priv->hclock); in sdhci_at91_probe()
443 static int sdhci_at91_remove(struct platform_device *pdev) in sdhci_at91_remove()
448 struct clk *gck = priv->gck; in sdhci_at91_remove()
449 struct clk *hclock = priv->hclock; in sdhci_at91_remove()
450 struct clk *mainck = priv->mainck; in sdhci_at91_remove()
452 pm_runtime_get_sync(&pdev->dev); in sdhci_at91_remove()
453 pm_runtime_disable(&pdev->dev); in sdhci_at91_remove()
454 pm_runtime_put_noidle(&pdev->dev); in sdhci_at91_remove()
467 .name = "sdhci-at91",