Lines Matching +full:power +full:- +full:stable +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
77 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
96 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
107 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
130 * struct sdhci_arasan_data - Arasan Controller Data
160 * internal clock even when the clock isn't stable */
178 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
184 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
196 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
215 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; in sdhci_arasan_syscon_write()
216 u32 reg = fld->reg; in sdhci_arasan_syscon_write()
217 u16 width = fld->width; in sdhci_arasan_syscon_write()
218 s16 shift = fld->shift; in sdhci_arasan_syscon_write()
228 return -EINVAL; in sdhci_arasan_syscon_write()
230 if (sdhci_arasan->soc_ctl_map->hiword_update) in sdhci_arasan_syscon_write()
242 mmc_hostname(host->mmc), ret); in sdhci_arasan_syscon_write()
251 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clock()
254 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
255 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
257 * If PHY off, set clock to max speed and power PHY on. in sdhci_arasan_set_clock()
259 * Although PHY docs apparently suggest power cycling in sdhci_arasan_set_clock()
266 * do is to power it on at a faster speed and then slam in sdhci_arasan_set_clock()
267 * through low speeds without power cycling. in sdhci_arasan_set_clock()
269 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
270 phy_power_on(sdhci_arasan->phy); in sdhci_arasan_set_clock()
271 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
280 * At higher clock speeds the PHY is fine being power in sdhci_arasan_set_clock()
281 * cycled and docs say you _should_ power cycle when in sdhci_arasan_set_clock()
288 if (ctrl_phy && sdhci_arasan->is_phy_on) { in sdhci_arasan_set_clock()
289 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_set_clock()
290 sdhci_arasan->is_phy_on = false; in sdhci_arasan_set_clock()
294 if (clk_data->set_clk_delays) in sdhci_arasan_set_clock()
295 clk_data->set_clk_delays(host); in sdhci_arasan_set_clock()
299 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) in sdhci_arasan_set_clock()
303 * stable. Trying to use a clock without waiting here results in sdhci_arasan_set_clock()
310 phy_power_on(sdhci_arasan->phy); in sdhci_arasan_set_clock()
311 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
322 if (ios->enhanced_strobe) in sdhci_arasan_hs400_enhanced_strobe()
338 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { in sdhci_arasan_reset()
348 switch (ios->signal_voltage) { in sdhci_arasan_voltage_switch()
364 return -EINVAL; in sdhci_arasan_voltage_switch()
385 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_arasan_cqhci_irq()
435 * sdhci_arasan_suspend - Suspend method for the driver
438 * Put the device in a low power state.
449 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_arasan_suspend()
450 mmc_retune_needed(host->mmc); in sdhci_arasan_suspend()
452 if (sdhci_arasan->has_cqe) { in sdhci_arasan_suspend()
453 ret = cqhci_suspend(host->mmc); in sdhci_arasan_suspend()
462 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { in sdhci_arasan_suspend()
463 ret = phy_power_off(sdhci_arasan->phy); in sdhci_arasan_suspend()
465 dev_err(dev, "Cannot power off phy.\n"); in sdhci_arasan_suspend()
469 sdhci_arasan->is_phy_on = false; in sdhci_arasan_suspend()
472 clk_disable(pltfm_host->clk); in sdhci_arasan_suspend()
473 clk_disable(sdhci_arasan->clk_ahb); in sdhci_arasan_suspend()
479 * sdhci_arasan_resume - Resume method for the driver
493 ret = clk_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_resume()
499 ret = clk_enable(pltfm_host->clk); in sdhci_arasan_resume()
505 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { in sdhci_arasan_resume()
506 ret = phy_power_on(sdhci_arasan->phy); in sdhci_arasan_resume()
508 dev_err(dev, "Cannot power on phy.\n"); in sdhci_arasan_resume()
511 sdhci_arasan->is_phy_on = true; in sdhci_arasan_resume()
520 if (sdhci_arasan->has_cqe) in sdhci_arasan_resume()
521 return cqhci_resume(host->mmc); in sdhci_arasan_resume()
531 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
548 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sdcardclk_recalc_rate()
550 return host->mmc->actual_clock; in sdhci_arasan_sdcardclk_recalc_rate()
558 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
575 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sampleclk_recalc_rate()
577 return host->mmc->actual_clock; in sdhci_arasan_sampleclk_recalc_rate()
585 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
588 * @degrees: The clock phase shift between 0 - 359.
600 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sdcardclk_set_phase()
607 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sdcardclk_set_phase()
610 switch (host->timing) { in sdhci_zynqmp_sdcardclk_set_phase()
650 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
653 * @degrees: The clock phase shift between 0 - 359.
665 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sampleclk_set_phase()
672 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sampleclk_set_phase()
678 switch (host->timing) { in sdhci_zynqmp_sampleclk_set_phase()
715 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
718 * @degrees: The clock phase shift between 0 - 359.
730 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sdcardclk_set_phase()
734 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sdcardclk_set_phase()
737 switch (host->timing) { in sdhci_versal_sdcardclk_set_phase()
781 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
784 * @degrees: The clock phase shift between 0 - 359.
796 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sampleclk_set_phase()
800 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sampleclk_set_phase()
803 switch (host->timing) { in sdhci_versal_sampleclk_set_phase()
871 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in arasan_zynqmp_execute_tuning()
889 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
898 * - Many existing devices don't seem to do this and work fine. To keep
902 * - The value of corecfg_clockmultiplier should sync with that of corresponding
904 * once at probe time and never called again.
912 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_clockmultiplier()
919 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_clockmultiplier()
920 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_clockmultiplier()
921 mmc_hostname(host->mmc)); in sdhci_arasan_update_clockmultiplier()
925 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); in sdhci_arasan_update_clockmultiplier()
929 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
937 * - Many existing devices don't seem to do this and work fine. To keep
941 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
943 * at probe time and never called again.
950 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_baseclkfreq()
951 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq()
958 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_baseclkfreq()
959 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_baseclkfreq()
960 mmc_hostname(host->mmc)); in sdhci_arasan_update_baseclkfreq()
964 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
971 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clk_delays()
973 clk_set_phase(clk_data->sampleclk, in sdhci_arasan_set_clk_delays()
974 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
975 clk_set_phase(clk_data->sdcardclk, in sdhci_arasan_set_clk_delays()
976 clk_data->clk_phase_out[host->timing]); in sdhci_arasan_set_clk_delays()
983 struct device_node *np = dev->of_node; in arasan_dt_read_clk_phase()
989 * Tap Values then use the pre-defined values. in arasan_dt_read_clk_phase()
994 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
995 clk_data->clk_phase_out[timing]); in arasan_dt_read_clk_phase()
1000 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1001 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
1005 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1023 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; in arasan_dt_parse_clk_phases()
1025 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { in arasan_dt_parse_clk_phases()
1031 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); in arasan_dt_parse_clk_phases()
1038 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1039 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1043 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { in arasan_dt_parse_clk_phases()
1050 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1051 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1056 "clk-phase-legacy"); in arasan_dt_parse_clk_phases()
1058 "clk-phase-mmc-hs"); in arasan_dt_parse_clk_phases()
1060 "clk-phase-sd-hs"); in arasan_dt_parse_clk_phases()
1062 "clk-phase-uhs-sdr12"); in arasan_dt_parse_clk_phases()
1064 "clk-phase-uhs-sdr25"); in arasan_dt_parse_clk_phases()
1066 "clk-phase-uhs-sdr50"); in arasan_dt_parse_clk_phases()
1068 "clk-phase-uhs-sdr104"); in arasan_dt_parse_clk_phases()
1070 "clk-phase-uhs-ddr50"); in arasan_dt_parse_clk_phases()
1072 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
1074 "clk-phase-mmc-hs200"); in arasan_dt_parse_clk_phases()
1076 "clk-phase-mmc-hs400"); in arasan_dt_parse_clk_phases()
1205 /* SoC-specific compatible strings w/ soc_ctl_map */
1207 .compatible = "rockchip,rk3399-sdhci-5.1",
1211 .compatible = "intel,lgm-sdhci-5.1-emmc",
1215 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1219 .compatible = "intel,keembay-sdhci-5.1-emmc",
1223 .compatible = "intel,keembay-sdhci-5.1-sd",
1227 .compatible = "intel,keembay-sdhci-5.1-sdio",
1232 .compatible = "arasan,sdhci-8.9a",
1236 .compatible = "arasan,sdhci-5.1",
1240 .compatible = "arasan,sdhci-4.9a",
1244 .compatible = "xlnx,zynqmp-8.9a",
1248 .compatible = "xlnx,versal-8.9a",
1256 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1273 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sdcardclk()
1274 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdcardclk()
1279 ret = of_property_read_string_index(np, "clock-output-names", 0, in sdhci_arasan_register_sdcardclk()
1282 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sdcardclk()
1290 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; in sdhci_arasan_register_sdcardclk()
1292 clk_data->sdcardclk_hw.init = &sdcardclk_init; in sdhci_arasan_register_sdcardclk()
1293 clk_data->sdcardclk = in sdhci_arasan_register_sdcardclk()
1294 devm_clk_register(dev, &clk_data->sdcardclk_hw); in sdhci_arasan_register_sdcardclk()
1295 if (IS_ERR(clk_data->sdcardclk)) in sdhci_arasan_register_sdcardclk()
1296 return PTR_ERR(clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1297 clk_data->sdcardclk_hw.init = NULL; in sdhci_arasan_register_sdcardclk()
1300 clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1308 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1325 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sampleclk()
1326 struct device_node *np = dev->of_node; in sdhci_arasan_register_sampleclk()
1331 ret = of_property_read_string_index(np, "clock-output-names", 1, in sdhci_arasan_register_sampleclk()
1334 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sampleclk()
1342 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; in sdhci_arasan_register_sampleclk()
1344 clk_data->sampleclk_hw.init = &sampleclk_init; in sdhci_arasan_register_sampleclk()
1345 clk_data->sampleclk = in sdhci_arasan_register_sampleclk()
1346 devm_clk_register(dev, &clk_data->sampleclk_hw); in sdhci_arasan_register_sampleclk()
1347 if (IS_ERR(clk_data->sampleclk)) in sdhci_arasan_register_sampleclk()
1348 return PTR_ERR(clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1349 clk_data->sampleclk_hw.init = NULL; in sdhci_arasan_register_sampleclk()
1352 clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1360 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1364 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1369 struct device_node *np = dev->of_node; in sdhci_arasan_unregister_sdclk()
1371 if (!of_find_property(np, "#clock-cells", NULL)) in sdhci_arasan_unregister_sdclk()
1374 of_clk_del_provider(dev->of_node); in sdhci_arasan_unregister_sdclk()
1378 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1381 * 0: the Core supports only 32-bit System Address Bus.
1382 * 1: the Core supports 64-bit System Address Bus.
1385 * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1386 * Keem Bay does not support 64-bit access.
1396 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_support64b()
1403 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_support64b()
1404 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_support64b()
1405 mmc_hostname(host->mmc)); in sdhci_arasan_update_support64b()
1409 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); in sdhci_arasan_update_support64b()
1413 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1423 * Note: without seriously re-architecting SDHCI's clock code and testing on
1429 * re-architecting SDHCI if we see some benefit to it.
1437 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdclk()
1442 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) in sdhci_arasan_register_sdclk()
1463 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_add_host()
1468 if (!sdhci_arasan->has_cqe) in sdhci_arasan_add_host()
1475 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host()
1478 ret = -ENOMEM; in sdhci_arasan_add_host()
1482 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host()
1483 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host()
1485 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_arasan_add_host()
1487 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host()
1489 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
1513 struct device_node *np = pdev->dev.of_node; in sdhci_arasan_probe()
1516 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); in sdhci_arasan_probe()
1517 data = match->data; in sdhci_arasan_probe()
1518 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); in sdhci_arasan_probe()
1525 sdhci_arasan->host = host; in sdhci_arasan_probe()
1527 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; in sdhci_arasan_probe()
1528 sdhci_arasan->clk_ops = data->clk_ops; in sdhci_arasan_probe()
1530 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); in sdhci_arasan_probe()
1532 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); in sdhci_arasan_probe()
1535 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { in sdhci_arasan_probe()
1536 ret = dev_err_probe(&pdev->dev, in sdhci_arasan_probe()
1537 PTR_ERR(sdhci_arasan->soc_ctl_base), in sdhci_arasan_probe()
1543 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); in sdhci_arasan_probe()
1544 if (IS_ERR(sdhci_arasan->clk_ahb)) { in sdhci_arasan_probe()
1545 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); in sdhci_arasan_probe()
1546 ret = PTR_ERR(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1550 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); in sdhci_arasan_probe()
1552 dev_err(&pdev->dev, "clk_xin clock not found.\n"); in sdhci_arasan_probe()
1557 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1559 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); in sdhci_arasan_probe()
1565 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); in sdhci_arasan_probe()
1571 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) in sdhci_arasan_probe()
1572 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; in sdhci_arasan_probe()
1574 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) in sdhci_arasan_probe()
1575 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; in sdhci_arasan_probe()
1577 pltfm_host->clk = clk_xin; in sdhci_arasan_probe()
1579 if (of_device_is_compatible(pdev->dev.of_node, in sdhci_arasan_probe()
1580 "rockchip,rk3399-sdhci-5.1")) in sdhci_arasan_probe()
1583 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || in sdhci_arasan_probe()
1584 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || in sdhci_arasan_probe()
1585 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { in sdhci_arasan_probe()
1589 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in sdhci_arasan_probe()
1594 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); in sdhci_arasan_probe()
1598 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1599 host->mmc_host_ops.execute_tuning = in sdhci_arasan_probe()
1603 arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); in sdhci_arasan_probe()
1605 ret = mmc_of_parse(host->mmc); in sdhci_arasan_probe()
1607 if (ret != -EPROBE_DEFER) in sdhci_arasan_probe()
1608 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); in sdhci_arasan_probe()
1612 sdhci_arasan->phy = ERR_PTR(-ENODEV); in sdhci_arasan_probe()
1613 if (of_device_is_compatible(pdev->dev.of_node, in sdhci_arasan_probe()
1614 "arasan,sdhci-5.1")) { in sdhci_arasan_probe()
1615 sdhci_arasan->phy = devm_phy_get(&pdev->dev, in sdhci_arasan_probe()
1617 if (IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_probe()
1618 ret = PTR_ERR(sdhci_arasan->phy); in sdhci_arasan_probe()
1619 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); in sdhci_arasan_probe()
1623 ret = phy_init(sdhci_arasan->phy); in sdhci_arasan_probe()
1625 dev_err(&pdev->dev, "phy_init err.\n"); in sdhci_arasan_probe()
1629 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_arasan_probe()
1631 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_arasan_probe()
1633 sdhci_arasan->has_cqe = true; in sdhci_arasan_probe()
1634 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_arasan_probe()
1636 if (!of_property_read_bool(np, "disable-cqe-dcmd")) in sdhci_arasan_probe()
1637 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; in sdhci_arasan_probe()
1647 if (!IS_ERR(sdhci_arasan->phy)) in sdhci_arasan_probe()
1648 phy_exit(sdhci_arasan->phy); in sdhci_arasan_probe()
1650 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_probe()
1654 clk_disable_unprepare(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1666 struct clk *clk_ahb = sdhci_arasan->clk_ahb; in sdhci_arasan_remove()
1668 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_remove()
1669 if (sdhci_arasan->is_phy_on) in sdhci_arasan_remove()
1670 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_remove()
1671 phy_exit(sdhci_arasan->phy); in sdhci_arasan_remove()
1674 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_remove()
1685 .name = "sdhci-arasan",