Lines Matching +full:imx7ulp +full:- +full:usdhc
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
133 * open ended multi-blk IO. Otherwise the TC INT wouldn't
143 * The flag tells that the ESDHC controller is an USDHC block that is
155 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
167 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
301 .name = "sdhci-esdhc-imx25",
304 .name = "sdhci-esdhc-imx35",
307 .name = "sdhci-esdhc-imx51",
316 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
317 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
318 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
319 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
320 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
321 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
322 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
323 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
324 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
325 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
326 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
327 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
328 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
335 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
340 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
345 return data->socdata == &usdhc_imx6q_data; in is_imx6q_usdhc()
350 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
355 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
361 #define DRIVER_NAME "sdhci-esdhc-imx"
363 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
382 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
394 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
396 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
397 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
404 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
410 /* move dat[0-3] bits */ in esdhc_readl_le()
417 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
418 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
436 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
437 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
446 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in esdhc_readl_le()
453 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || in esdhc_readl_le()
454 IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
477 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
480 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
482 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
502 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
504 * re-sample it by the following steps. in esdhc_writel_le()
506 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
508 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
510 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
519 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
523 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
525 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
527 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
532 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
533 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
537 writel(val, host->ioaddr + reg); in esdhc_writel_le()
551 * The usdhc register returns a wrong host version. in esdhc_readw_le()
559 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
564 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
565 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
566 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
568 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
583 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
591 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
597 return readw(host->ioaddr + reg); in esdhc_readw_le()
608 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
613 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
618 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
623 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
624 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_writew_le()
625 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
633 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
634 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
635 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
636 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
653 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
654 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
658 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
659 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
660 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
661 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
663 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
665 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
670 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
677 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
683 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
693 * tuning, when send tuning command, usdhc will in esdhc_writew_le()
706 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
712 imx_data->scratchpad = val; in esdhc_writew_le()
716 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
719 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
720 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
721 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
725 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
727 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
728 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
744 val = readl(host->ioaddr + reg); in esdhc_readb_le()
753 return readb(host->ioaddr + reg); in esdhc_readb_le()
793 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
811 * The reset on usdhc fails to clear MIX_CTRL register. in esdhc_writeb_le()
818 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
820 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
821 imx_data->is_ddr = 0; in esdhc_writeb_le()
839 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
846 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
854 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
855 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
862 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
864 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
869 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
879 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
880 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
881 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
882 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
892 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { in esdhc_pltfm_set_clock()
895 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
907 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
908 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
909 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
912 div--; in esdhc_pltfm_set_clock()
921 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
923 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
924 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
927 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
929 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
938 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
940 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
942 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
944 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
950 return -ENOSYS; in esdhc_pltfm_get_ro()
978 * i.MX uSDHC internally already uses a fixed optimized timing for in usdhc_execute_tuning()
981 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
996 /* IC suggest to reset USDHC before every tuning command */ in esdhc_prepare_tuning()
998 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
1000 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
1001 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1004 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1007 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1008 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
1009 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1011 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1018 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1021 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1032 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1041 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1042 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1051 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1054 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1065 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1066 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1070 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1080 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1082 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1083 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1084 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1085 return -EINVAL; in esdhc_change_pinstate()
1090 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1095 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1099 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1102 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1123 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1125 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1130 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1132 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1136 * for the uSDHC loopback read clock in esdhc_set_strobe_dll()
1138 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1139 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1145 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1148 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1150 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1151 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1163 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1164 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1167 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1168 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1169 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1170 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1172 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1182 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1185 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1187 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1196 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1201 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1202 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1203 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1205 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1210 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1215 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1216 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1218 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1243 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ in esdhc_get_max_timeout_count()
1266 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1303 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1311 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1315 * to zero if this usdhc is chosen to boot system. Change in sdhci_esdhc_imx_hwinit()
1324 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1326 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1332 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1333 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1336 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1340 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a in sdhci_esdhc_imx_hwinit()
1347 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1348 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1350 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1352 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1355 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1356 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1359 if (imx_data->boarddata.tuning_start_tap) { in sdhci_esdhc_imx_hwinit()
1361 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1364 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1366 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1375 * the buffer read ready interrupt immediately. If usdhc send in sdhci_esdhc_imx_hwinit()
1381 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1382 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1388 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1390 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1413 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1426 if (count-- == 0) { in esdhc_cqe_enable()
1427 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1440 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1442 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1454 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1478 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1479 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1482 if (of_get_property(np, "fsl,wp-controller", NULL)) in sdhci_esdhc_imx_probe_dt()
1483 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1490 if (of_property_read_bool(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1491 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1493 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1494 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1495 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1497 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1498 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1499 if (of_find_property(np, "no-1-8-v", NULL)) in sdhci_esdhc_imx_probe_dt()
1500 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1502 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1503 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1505 mmc_of_parse_voltage(np, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1508 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1510 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1515 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1519 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1520 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1530 return -ENODEV; in sdhci_esdhc_imx_probe_dt()
1538 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_nondt()
1541 if (!host->mmc->parent->platform_data) { in sdhci_esdhc_imx_probe_nondt()
1542 dev_err(mmc_dev(host->mmc), "no board data!\n"); in sdhci_esdhc_imx_probe_nondt()
1543 return -EINVAL; in sdhci_esdhc_imx_probe_nondt()
1546 imx_data->boarddata = *((struct esdhc_platform_data *) in sdhci_esdhc_imx_probe_nondt()
1547 host->mmc->parent->platform_data); in sdhci_esdhc_imx_probe_nondt()
1549 if (boarddata->wp_type == ESDHC_WP_GPIO) { in sdhci_esdhc_imx_probe_nondt()
1550 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; in sdhci_esdhc_imx_probe_nondt()
1552 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0); in sdhci_esdhc_imx_probe_nondt()
1554 dev_err(mmc_dev(host->mmc), in sdhci_esdhc_imx_probe_nondt()
1555 "failed to request write-protect gpio!\n"); in sdhci_esdhc_imx_probe_nondt()
1561 switch (boarddata->cd_type) { in sdhci_esdhc_imx_probe_nondt()
1563 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0); in sdhci_esdhc_imx_probe_nondt()
1565 dev_err(mmc_dev(host->mmc), in sdhci_esdhc_imx_probe_nondt()
1566 "failed to request card-detect gpio!\n"); in sdhci_esdhc_imx_probe_nondt()
1573 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_nondt()
1577 host->mmc->caps |= MMC_CAP_NONREMOVABLE; in sdhci_esdhc_imx_probe_nondt()
1584 switch (boarddata->max_bus_width) { in sdhci_esdhc_imx_probe_nondt()
1586 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1589 host->mmc->caps |= MMC_CAP_4_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1593 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1603 of_match_device(imx_esdhc_dt_ids, &pdev->dev); in sdhci_esdhc_imx_probe()
1619 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) in sdhci_esdhc_imx_probe()
1620 pdev->id_entry->driver_data; in sdhci_esdhc_imx_probe()
1622 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1623 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1625 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1626 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1627 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1631 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1632 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1633 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1637 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1638 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1639 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1643 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1644 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1645 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1648 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1651 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1655 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1656 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1657 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1660 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1661 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1664 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1666 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1667 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1670 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1671 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1672 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1675 * Link usdhc specific mmc_host_ops execute_tuning function, in sdhci_esdhc_imx_probe()
1678 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1681 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1685 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1686 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1688 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1689 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; in sdhci_esdhc_imx_probe()
1691 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1692 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1694 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1695 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1696 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1700 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1701 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1702 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1704 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1708 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1709 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1711 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1729 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1730 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1731 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1732 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1733 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1738 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1740 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1742 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1744 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1745 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1755 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1757 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1758 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1759 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1763 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1764 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1765 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1767 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1768 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1783 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1784 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1789 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1790 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1791 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1792 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1795 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1796 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1806 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1820 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1827 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1828 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1831 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1845 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1846 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1855 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1856 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1858 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1860 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1861 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1862 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1864 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1865 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1877 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1878 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1880 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1881 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1883 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1887 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1891 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1895 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1901 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
1902 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
1907 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1909 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1911 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1913 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1914 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
1927 .name = "sdhci-esdhc-imx",