47 #define OMAP_HSMMC_SYSSTATUS	0x0014
48 #define OMAP_HSMMC_CON		0x002C
49 #define OMAP_HSMMC_SDMASA	0x0100
50 #define OMAP_HSMMC_BLK		0x0104
51 #define OMAP_HSMMC_ARG		0x0108
52 #define OMAP_HSMMC_CMD		0x010C
53 #define OMAP_HSMMC_RSP10	0x0110
54 #define OMAP_HSMMC_RSP32	0x0114
55 #define OMAP_HSMMC_RSP54	0x0118
56 #define OMAP_HSMMC_RSP76	0x011C
57 #define OMAP_HSMMC_DATA		0x0120
58 #define OMAP_HSMMC_PSTATE	0x0124
59 #define OMAP_HSMMC_HCTL		0x0128
60 #define OMAP_HSMMC_SYSCTL	0x012C
61 #define OMAP_HSMMC_STAT		0x0130
62 #define OMAP_HSMMC_IE		0x0134
63 #define OMAP_HSMMC_ISE		0x0138
64 #define OMAP_HSMMC_AC12		0x013C
65 #define OMAP_HSMMC_CAPA		0x0140
70 #define SDVS18			(0x5 << 9)
71 #define SDVS30			(0x6 << 9)
72 #define SDVS33			(0x7 << 9)
73 #define SDVS_MASK		0x00000E00
74 #define SDVSCLR			0xFFFFF1FF
75 #define SDVSDET			0x00000400
76 #define AUTOIDLE		0x1
78 #define DTO			0xe
79 #define ICE			0x1
80 #define ICS			0x2
82 #define CLKD_MAX		0x3FF		/* max clock divisor: 1023 */
83 #define CLKD_MASK		0x0000FFC0
85 #define DTO_MASK		0x000F0000
91 #define DMAE			0x1
101 #define OD			0x1
102 #define STAT_CLEAR		0xFFFFFFFF
103 #define INIT_STREAM_CMD		0x00000000
113 #define CC_EN			(1 << 0)
139 #define ACNE	(1 << 0)
203 #define AUTO_CMD23		(1 << 0)        /* Auto CMD23 support */
238 	return 0;  in omap_hsmmc_enable_supply()
242 		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);  in omap_hsmmc_enable_supply()
259 		host->vqmmc_enabled = 0;  in omap_hsmmc_disable_supply()
263 		ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);  in omap_hsmmc_disable_supply()
268 	return 0;  in omap_hsmmc_disable_supply()
285 		return 0;  in omap_hsmmc_set_pbias()
288 		if (host->pbias_enabled == 0) {  in omap_hsmmc_set_pbias()
303 			host->pbias_enabled = 0;  in omap_hsmmc_set_pbias()
307 	return 0;  in omap_hsmmc_set_pbias()
313 	int ret = 0;  in omap_hsmmc_set_power()
320 		return 0;  in omap_hsmmc_set_power()
353 	return 0;  in omap_hsmmc_set_power()
366 		return 0;  in omap_hsmmc_disable_boot_regulator()
378 	return 0;  in omap_hsmmc_disable_boot_regulator()
411 	return 0;  in omap_hsmmc_disable_boot_regulators()
451 		return 0;  in omap_hsmmc_reg_get()
457 	return 0;  in omap_hsmmc_reg_get()
476 	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)  in omap_hsmmc_stop_clock()
506 	u32 irq_mask = 0;  in omap_hsmmc_disable_irq()
522 	u16 dsor = 0;  in calc_divisor()
639 		return 0;  in omap_hsmmc_context_restore()
672 	OMAP_HSMMC_WRITE(host->base, ISE, 0);  in omap_hsmmc_context_restore()
673 	OMAP_HSMMC_WRITE(host->base, IE, 0);  in omap_hsmmc_context_restore()
689 	return 0;  in omap_hsmmc_context_restore()
707 	return 0;  in omap_hsmmc_context_restore()
722 	int reg = 0;  in send_init_stream()
764 	int cmdreg = 0, resptype = 0, cmdtype = 0;  in omap_hsmmc_start_command()
766 	dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",  in omap_hsmmc_start_command()
772 	host->response_busy = 0;  in omap_hsmmc_start_command()
786 	 * a val of 0x3, rest 0x0.  in omap_hsmmc_start_command()
789 		cmdtype = 0x3;  in omap_hsmmc_start_command()
827 	host->req_in_progress = 0;  in omap_hsmmc_request_done()
851 			host->response_busy = 0;  in omap_hsmmc_xfer_done()
864 		data->bytes_xfered = 0;  in omap_hsmmc_xfer_done()
895 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);  in omap_hsmmc_cmd_done()
898 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);  in omap_hsmmc_cmd_done()
928 		host->data->host_cookie = 0;  in omap_hsmmc_dma_cleanup()
950 	len = sprintf(buf, "MMC IRQ 0x%x :", status);  in omap_hsmmc_dbg_report_irq()
953 	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)  in omap_hsmmc_dbg_report_irq()
978 	unsigned long i = 0;  in omap_hsmmc_reset_controller_fsm()
986 	 * Monitor a 0->1 transition first  in omap_hsmmc_reset_controller_fsm()
993 	i = 0;  in omap_hsmmc_reset_controller_fsm()
1024 	int end_cmd = 0, end_trans = 0;  in omap_hsmmc_do_irq()
1025 	int error = 0;  in omap_hsmmc_do_irq()
1037 			host->response_busy = 0;  in omap_hsmmc_do_irq()
1057 			dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);  in omap_hsmmc_do_irq()
1097 	for (i = 0; i < loops_per_jiffy; i++) {  in set_sd_bus_power()
1113 	u32 reg_val = 0;  in omap_hsmmc_switch_opcond()
1120 	ret = omap_hsmmc_set_power(host, 0);  in omap_hsmmc_switch_opcond()
1127 	if (ret != 0)  in omap_hsmmc_switch_opcond()
1157 	return 0;  in omap_hsmmc_switch_opcond()
1171 	if (host->dma_ch < 0) {  in omap_hsmmc_dma_callback()
1208 		data->host_cookie = 0;  in omap_hsmmc_pre_dma_transfer()
1218 		host->next_data.dma_len = 0;  in omap_hsmmc_pre_dma_transfer()
1222 	if (dma_len == 0)  in omap_hsmmc_pre_dma_transfer()
1227 		data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;  in omap_hsmmc_pre_dma_transfer()
1231 	return 0;  in omap_hsmmc_pre_dma_transfer()
1241 	int ret = 0, i;  in omap_hsmmc_setup_dma_transfer()
1254 	for (i = 0; i < data->sg_len; i++) {  in omap_hsmmc_setup_dma_transfer()
1261 	if ((data->blksz % 4) != 0)  in omap_hsmmc_setup_dma_transfer()
1296 	return 0;  in omap_hsmmc_setup_dma_transfer()
1305 	uint32_t reg, clkd, dto = 0;  in set_data_timeout()
1309 	if (clkd == 0)  in set_data_timeout()
1316 		while ((timeout & 0x80000000) == 0) {  in set_data_timeout()
1327 			dto = 0;  in set_data_timeout()
1364 		OMAP_HSMMC_WRITE(host->base, BLK, 0);  in omap_hsmmc_prepare_data()
1375 			set_data_timeout(host, timeout, 0);  in omap_hsmmc_prepare_data()
1377 		return 0;  in omap_hsmmc_prepare_data()
1382 		if (ret != 0) {  in omap_hsmmc_prepare_data()
1387 	return 0;  in omap_hsmmc_prepare_data()
1401 		data->host_cookie = 0;  in omap_hsmmc_post_req()
1410 		mrq->data->host_cookie = 0;  in omap_hsmmc_pre_req()
1419 			mrq->data->host_cookie = 0;  in omap_hsmmc_pre_req()
1434 		host->reqs_blocked = 0;  in omap_hsmmc_request()
1460 	int do_send_init_stream = 0;  in omap_hsmmc_set_ios()
1465 			omap_hsmmc_set_power(host, 0);  in omap_hsmmc_set_ios()
1493 			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)  in omap_hsmmc_set_ios()
1532 			card->cis.vendor = 0x104c;  in omap_hsmmc_init_card()
1533 			card->cis.device = 0x9066;  in omap_hsmmc_init_card()
1536 			card->ocr = 0x80;  in omap_hsmmc_init_card()
1618 	return 0;  in omap_hsmmc_configure_wake_irq()
1624 	host->wake_irq = 0;  in omap_hsmmc_configure_wake_irq()
1710 	return 0;  in mmc_regs_show()
1737 	.reg_offset = 0x100,
1740 	.reg_offset = 0x100,
1834 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in omap_hsmmc_probe()
1835 	irq = platform_get_irq(pdev, 0);  in omap_hsmmc_probe()
1836 	if (res == NULL || irq < 0)  in omap_hsmmc_probe()
1864 	host->pbias_enabled = 0;  in omap_hsmmc_probe()
1865 	host->vqmmc_enabled = 0;  in omap_hsmmc_probe()
1876 	if (pdata->max_freq > 0)  in omap_hsmmc_probe()
1878 	else if (mmc->f_max == 0)  in omap_hsmmc_probe()
1909 	} else if (clk_prepare_enable(host->dbclk) != 0) {  in omap_hsmmc_probe()
1919 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */  in omap_hsmmc_probe()
1962 	ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,  in omap_hsmmc_probe()
1994 		if (ret < 0)  in omap_hsmmc_probe()
2002 	return 0;  in omap_hsmmc_probe()
2041 	return 0;  in omap_hsmmc_remove()
2050 		return 0;  in omap_hsmmc_suspend()
2055 		OMAP_HSMMC_WRITE(host->base, ISE, 0);  in omap_hsmmc_suspend()
2056 		OMAP_HSMMC_WRITE(host->base, IE, 0);  in omap_hsmmc_suspend()
2065 	return 0;  in omap_hsmmc_suspend()
2074 		return 0;  in omap_hsmmc_resume()
2085 	return 0;  in omap_hsmmc_resume()
2093 	int ret = 0;  in omap_hsmmc_runtime_suspend()
2103 		OMAP_HSMMC_WRITE(host->base, ISE, 0);  in omap_hsmmc_runtime_suspend()
2104 		OMAP_HSMMC_WRITE(host->base, IE, 0);  in omap_hsmmc_runtime_suspend()
2154 	return 0;  in omap_hsmmc_runtime_resume()