Lines Matching +full:hw +full:- +full:settle +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2020, Intel Corporation. All rights reserved.
18 #include "hw-txe.h"
22 #include "mei-trace.h"
27 * mei_txe_reg_read - Reads 32bit data from the txe device
41 * mei_txe_reg_write - Writes 32bit data to the txe device
54 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
56 * @hw: the txe hardware structure
63 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, in mei_txe_sec_reg_read_silent() argument
66 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); in mei_txe_sec_reg_read_silent()
70 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
72 * @hw: the txe hardware structure
79 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, in mei_txe_sec_reg_read() argument
82 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); in mei_txe_sec_reg_read()
83 return mei_txe_sec_reg_read_silent(hw, offset); in mei_txe_sec_reg_read()
86 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
89 * @hw: the txe hardware structure
95 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, in mei_txe_sec_reg_write_silent() argument
98 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); in mei_txe_sec_reg_write_silent()
102 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
104 * @hw: the txe hardware structure
110 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, in mei_txe_sec_reg_write() argument
113 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); in mei_txe_sec_reg_write()
114 mei_txe_sec_reg_write_silent(hw, offset, value); in mei_txe_sec_reg_write()
117 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
119 * @hw: the txe hardware structure
124 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, in mei_txe_br_reg_read() argument
127 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); in mei_txe_br_reg_read()
131 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
133 * @hw: the txe hardware structure
137 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, in mei_txe_br_reg_write() argument
140 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); in mei_txe_br_reg_write()
144 * mei_txe_aliveness_set - request for aliveness change
153 * Locking: called under "dev->device_lock" lock
160 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_set() local
161 bool do_req = hw->aliveness != req; in mei_txe_aliveness_set()
163 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", in mei_txe_aliveness_set()
164 hw->aliveness, req); in mei_txe_aliveness_set()
166 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_txe_aliveness_set()
167 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); in mei_txe_aliveness_set()
174 * mei_txe_aliveness_req_get - get aliveness requested register value
185 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_req_get() local
188 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); in mei_txe_aliveness_req_get()
193 * mei_txe_aliveness_get - get aliveness response register value
202 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_get() local
205 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); in mei_txe_aliveness_get()
210 * mei_txe_aliveness_poll - waits for aliveness to settle
217 * Return: 0 if the expected value was received, -ETIME otherwise
221 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_poll() local
227 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_poll()
228 if (hw->aliveness == expected) { in mei_txe_aliveness_poll()
229 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_poll()
230 dev_dbg(dev->dev, "aliveness settled after %lld usecs\n", in mei_txe_aliveness_poll()
237 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_poll()
238 dev_err(dev->dev, "aliveness timed out\n"); in mei_txe_aliveness_poll()
239 return -ETIME; in mei_txe_aliveness_poll()
243 * mei_txe_aliveness_wait - waits for aliveness to settle
254 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_wait() local
260 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_wait()
261 if (hw->aliveness == expected) in mei_txe_aliveness_wait()
264 mutex_unlock(&dev->device_lock); in mei_txe_aliveness_wait()
265 err = wait_event_timeout(hw->wait_aliveness_resp, in mei_txe_aliveness_wait()
266 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_txe_aliveness_wait()
267 mutex_lock(&dev->device_lock); in mei_txe_aliveness_wait()
269 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_wait()
270 ret = hw->aliveness == expected ? 0 : -ETIME; in mei_txe_aliveness_wait()
273 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", in mei_txe_aliveness_wait()
274 err, hw->aliveness, dev->pg_event); in mei_txe_aliveness_wait()
276 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", in mei_txe_aliveness_wait()
277 jiffies_to_msecs(timeout - err), in mei_txe_aliveness_wait()
278 hw->aliveness, dev->pg_event); in mei_txe_aliveness_wait()
280 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_wait()
285 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
300 * mei_txe_pg_in_transition - is device now in pg transition
308 return dev->pg_event == MEI_PG_EVENT_WAIT; in mei_txe_pg_in_transition()
312 * mei_txe_pg_is_enabled - detect if PG is supported by HW
324 * mei_txe_pg_state - translate aliveness register value
333 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_pg_state() local
335 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; in mei_txe_pg_state()
339 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
345 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_input_ready_interrupt_enable() local
348 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); in mei_txe_input_ready_interrupt_enable()
350 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); in mei_txe_input_ready_interrupt_enable()
354 * mei_txe_input_doorbell_set - sets bit 0 in
357 * @hw: the txe hardware structure
359 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) in mei_txe_input_doorbell_set() argument
362 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); in mei_txe_input_doorbell_set()
363 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); in mei_txe_input_doorbell_set()
367 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
369 * @hw: the txe hardware structure
371 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) in mei_txe_output_ready_set() argument
373 mei_txe_br_reg_write(hw, in mei_txe_output_ready_set()
379 * mei_txe_is_input_ready - check if TXE is ready for receiving data
387 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_is_input_ready() local
390 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); in mei_txe_is_input_ready()
395 * mei_txe_intr_clear - clear all interrupts
401 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_clear() local
403 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, in mei_txe_intr_clear()
405 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); in mei_txe_intr_clear()
406 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); in mei_txe_intr_clear()
410 * mei_txe_intr_disable - disable all interrupts
416 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_disable() local
418 mei_txe_br_reg_write(hw, HHIER_REG, 0); in mei_txe_intr_disable()
419 mei_txe_br_reg_write(hw, HIER_REG, 0); in mei_txe_intr_disable()
422 * mei_txe_intr_enable - enable all interrupts
428 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_enable() local
430 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); in mei_txe_intr_enable()
431 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); in mei_txe_intr_enable()
435 * mei_txe_synchronize_irq - wait for pending IRQ handlers
441 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_txe_synchronize_irq()
443 synchronize_irq(pdev->irq); in mei_txe_synchronize_irq()
447 * mei_txe_pending_interrupts - check if there are pending interrupts
460 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_pending_interrupts() local
461 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | in mei_txe_pending_interrupts()
467 dev_dbg(dev->dev, in mei_txe_pending_interrupts()
469 !!(hw->intr_cause & TXE_INTR_IN_READY), in mei_txe_pending_interrupts()
470 !!(hw->intr_cause & TXE_INTR_READINESS), in mei_txe_pending_interrupts()
471 !!(hw->intr_cause & TXE_INTR_ALIVENESS), in mei_txe_pending_interrupts()
472 !!(hw->intr_cause & TXE_INTR_OUT_DB)); in mei_txe_pending_interrupts()
478 * mei_txe_input_payload_write - write a dword to the host buffer
488 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_input_payload_write() local
490 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + in mei_txe_input_payload_write()
495 * mei_txe_out_data_read - read dword from the device buffer
506 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_out_data_read() local
508 return mei_txe_br_reg_read(hw, in mei_txe_out_data_read()
515 * mei_txe_readiness_set_host_rdy - set host readiness bit
521 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_set_host_rdy() local
523 mei_txe_br_reg_write(hw, in mei_txe_readiness_set_host_rdy()
529 * mei_txe_readiness_clear - clear host readiness bit
535 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_clear() local
537 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, in mei_txe_readiness_clear()
541 * mei_txe_readiness_get - Reads and returns
550 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_get() local
552 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); in mei_txe_readiness_get()
557 * mei_txe_readiness_is_sec_rdy - check readiness
570 * mei_txe_hw_is_ready - check if the hw is ready
584 * mei_txe_host_is_ready - check if the host is ready
592 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_host_is_ready() local
593 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); in mei_txe_host_is_ready()
599 * mei_txe_readiness_wait - wait till readiness settles
603 * Return: 0 on success and -ETIME on timeout
610 mutex_unlock(&dev->device_lock); in mei_txe_readiness_wait()
611 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, in mei_txe_readiness_wait()
613 mutex_lock(&dev->device_lock); in mei_txe_readiness_wait()
614 if (!dev->recvd_hw_ready) { in mei_txe_readiness_wait()
615 dev_err(dev->dev, "wait for readiness failed\n"); in mei_txe_readiness_wait()
616 return -ETIME; in mei_txe_readiness_wait()
619 dev->recvd_hw_ready = false; in mei_txe_readiness_wait()
630 * mei_txe_fw_status - read fw status register from pci config space
641 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_txe_fw_status()
646 return -EINVAL; in mei_txe_fw_status()
648 fw_status->count = fw_src->count; in mei_txe_fw_status()
649 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { in mei_txe_fw_status()
650 ret = pci_read_config_dword(pdev, fw_src->status[i], in mei_txe_fw_status()
651 &fw_status->status[i]); in mei_txe_fw_status()
652 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", in mei_txe_fw_status()
653 fw_src->status[i], in mei_txe_fw_status()
654 fw_status->status[i]); in mei_txe_fw_status()
663 * mei_txe_hw_config - configure hardware at the start of the devices
668 * once at the device probe time
675 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_config() local
677 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_hw_config()
678 hw->readiness = mei_txe_readiness_get(dev); in mei_txe_hw_config()
680 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", in mei_txe_hw_config()
681 hw->aliveness, hw->readiness); in mei_txe_hw_config()
687 * mei_txe_write - writes a message to device.
691 * @hdr_len: header length in bytes - must multiplication of a slot (4bytes)
695 * Return: 0 if success, < 0 - otherwise.
701 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_write() local
709 return -EINVAL; in mei_txe_write()
711 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_txe_write()
715 return -EMSGSIZE; in mei_txe_write()
717 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) in mei_txe_write()
718 return -EAGAIN; in mei_txe_write()
727 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str); in mei_txe_write()
728 return -EAGAIN; in mei_txe_write()
743 memcpy(®, (const u8 *)data + data_len - rem, rem); in mei_txe_write()
748 hw->slots = 0; in mei_txe_write()
750 /* Set Input-Doorbell */ in mei_txe_write()
751 mei_txe_input_doorbell_set(hw); in mei_txe_write()
757 * mei_txe_hbuf_depth - mimics the me hbuf circular buffer
769 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
777 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hbuf_empty_slots() local
779 return hw->slots; in mei_txe_hbuf_empty_slots()
783 * mei_txe_count_full_read_slots - mimics the me device circular buffer
796 * mei_txe_read_hdr - read message header which is always in 4 first bytes
808 * mei_txe_read - reads a message from the txe device.
814 * Return: -EINVAL on error wrong argument and 0 on success
820 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_read() local
826 return -EINVAL; in mei_txe_read()
831 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", in mei_txe_read()
837 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); in mei_txe_read()
846 mei_txe_output_ready_set(hw); in mei_txe_read()
851 * mei_txe_hw_reset - resets host and fw.
860 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_reset() local
867 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); in mei_txe_hw_reset()
870 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_hw_reset()
878 * Since we might have interrupts disabled - poll for it in mei_txe_hw_reset()
880 if (aliveness_req != hw->aliveness) in mei_txe_hw_reset()
882 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); in mei_txe_hw_reset()
883 return -EIO; in mei_txe_hw_reset()
892 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); in mei_txe_hw_reset()
893 return -EIO; in mei_txe_hw_reset()
906 * mei_txe_hw_start - start the hardware after reset
914 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_start() local
924 dev_err(dev->dev, "waiting for readiness failed\n"); in mei_txe_hw_start()
931 hisr = mei_txe_br_reg_read(hw, HISR_REG); in mei_txe_hw_start()
933 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); in mei_txe_hw_start()
936 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); in mei_txe_hw_start()
940 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); in mei_txe_hw_start()
944 pm_runtime_set_active(dev->dev); in mei_txe_hw_start()
953 mei_txe_output_ready_set(hw); in mei_txe_hw_start()
963 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
973 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_check_and_ack_intrs() local
981 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); in mei_txe_check_and_ack_intrs()
986 hisr = mei_txe_br_reg_read(hw, HISR_REG); in mei_txe_check_and_ack_intrs()
990 ipc_isr = mei_txe_sec_reg_read_silent(hw, in mei_txe_check_and_ack_intrs()
1003 hw->intr_cause |= hisr & HISR_INT_STS_MSK; in mei_txe_check_and_ack_intrs()
1005 hw->intr_cause |= TXE_INTR_IN_READY; in mei_txe_check_and_ack_intrs()
1011 mei_txe_sec_reg_write_silent(hw, in mei_txe_check_and_ack_intrs()
1013 mei_txe_br_reg_write(hw, HISR_REG, hisr); in mei_txe_check_and_ack_intrs()
1014 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); in mei_txe_check_and_ack_intrs()
1022 * mei_txe_irq_quick_handler - The ISR of the MEI device
1041 * mei_txe_irq_thread_handler - txe interrupt thread
1051 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_irq_thread_handler() local
1056 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", in mei_txe_irq_thread_handler()
1057 mei_txe_br_reg_read(hw, HHISR_REG), in mei_txe_irq_thread_handler()
1058 mei_txe_br_reg_read(hw, HISR_REG), in mei_txe_irq_thread_handler()
1059 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); in mei_txe_irq_thread_handler()
1063 mutex_lock(&dev->device_lock); in mei_txe_irq_thread_handler()
1066 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) in mei_txe_irq_thread_handler()
1072 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_irq_thread_handler()
1073 hw->readiness = mei_txe_readiness_get(dev); in mei_txe_irq_thread_handler()
1079 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1080 dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); in mei_txe_irq_thread_handler()
1083 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { in mei_txe_irq_thread_handler()
1084 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_txe_irq_thread_handler()
1085 dev->recvd_hw_ready = true; in mei_txe_irq_thread_handler()
1087 dev->recvd_hw_ready = false; in mei_txe_irq_thread_handler()
1088 if (dev->dev_state != MEI_DEV_RESETTING) { in mei_txe_irq_thread_handler()
1090 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_txe_irq_thread_handler()
1091 schedule_work(&dev->reset_work); in mei_txe_irq_thread_handler()
1096 wake_up(&dev->wait_hw_ready); in mei_txe_irq_thread_handler()
1105 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1107 dev_dbg(dev->dev, in mei_txe_irq_thread_handler()
1108 "Aliveness Interrupt: Status: %d\n", hw->aliveness); in mei_txe_irq_thread_handler()
1109 dev->pg_event = MEI_PG_EVENT_RECEIVED; in mei_txe_irq_thread_handler()
1110 if (waitqueue_active(&hw->wait_aliveness_resp)) in mei_txe_irq_thread_handler()
1111 wake_up(&hw->wait_aliveness_resp); in mei_txe_irq_thread_handler()
1119 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1123 (dev->dev_state != MEI_DEV_RESETTING && in mei_txe_irq_thread_handler()
1124 dev->dev_state != MEI_DEV_POWER_DOWN)) { in mei_txe_irq_thread_handler()
1125 dev_err(dev->dev, in mei_txe_irq_thread_handler()
1128 schedule_work(&dev->reset_work); in mei_txe_irq_thread_handler()
1133 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1134 dev->hbuf_is_ready = true; in mei_txe_irq_thread_handler()
1135 hw->slots = TXE_HBUF_DEPTH; in mei_txe_irq_thread_handler()
1138 if (hw->aliveness && dev->hbuf_is_ready) { in mei_txe_irq_thread_handler()
1140 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_txe_irq_thread_handler()
1142 if (rets && rets != -EMSGSIZE) in mei_txe_irq_thread_handler()
1143 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", in mei_txe_irq_thread_handler()
1145 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_txe_irq_thread_handler()
1151 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_txe_irq_thread_handler()
1153 mutex_unlock(&dev->device_lock); in mei_txe_irq_thread_handler()
1193 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1202 struct mei_txe_hw *hw; in mei_txe_dev_init() local
1204 dev = devm_kzalloc(&pdev->dev, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); in mei_txe_dev_init()
1208 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); in mei_txe_dev_init()
1210 hw = to_txe_hw(dev); in mei_txe_dev_init()
1212 init_waitqueue_head(&hw->wait_aliveness_resp); in mei_txe_dev_init()
1218 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1228 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_setup_satt2() local
1236 return -EINVAL; in mei_txe_setup_satt2()
1240 return -EINVAL; in mei_txe_setup_satt2()
1244 return -EINVAL; in mei_txe_setup_satt2()
1248 return -EINVAL; in mei_txe_setup_satt2()
1253 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); in mei_txe_setup_satt2()
1254 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); in mei_txe_setup_satt2()
1255 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); in mei_txe_setup_satt2()
1256 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", in mei_txe_setup_satt2()