140 	u32 hcsr;  in mei_hcsr_set_hig()  local
142 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_hcsr_set_hig()
143 	mei_hcsr_set(dev, hcsr);  in mei_hcsr_set_hig()
242 	u32 hcsr, reg;  in mei_me_hw_config()  local
248 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_config()
249 	hw->hbuf_depth = (hcsr & H_CBD) >> 24;  in mei_me_hw_config()
282 static inline u32 me_intr_src(u32 hcsr)  in me_intr_src()  argument
284 	return hcsr & H_CSR_IS_MASK;  in me_intr_src()
294 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)  in me_intr_disable()  argument
296 	hcsr &= ~H_CSR_IE_MASK;  in me_intr_disable()
297 	mei_hcsr_set(dev, hcsr);  in me_intr_disable()
306 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)  in me_intr_clear()  argument
308 	if (me_intr_src(hcsr))  in me_intr_clear()
309 		mei_hcsr_write(dev, hcsr);  in me_intr_clear()
319 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_clear()  local
321 	me_intr_clear(dev, hcsr);  in mei_me_intr_clear()
330 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_enable()  local
332 	hcsr |= H_CSR_IE_MASK;  in mei_me_intr_enable()
333 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_enable()
343 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_disable()  local
345 	me_intr_disable(dev, hcsr);  in mei_me_intr_disable()
367 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset_release()  local
369 	hcsr |= H_IG;  in mei_me_hw_reset_release()
370 	hcsr &= ~H_RST;  in mei_me_hw_reset_release()
371 	mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset_release()
381 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_set_ready()  local
383 	hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;  in mei_me_host_set_ready()
384 	mei_hcsr_set(dev, hcsr);  in mei_me_host_set_ready()
395 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_is_ready()  local
397 	return (hcsr & H_RDY) == H_RDY;  in mei_me_host_is_ready()
478 	u32 hcsr;  in mei_hbuf_filled_slots()  local
481 	hcsr = mei_hcsr_read(dev);  in mei_hbuf_filled_slots()
483 	read_ptr = (char) ((hcsr & H_CBRP) >> 8);  in mei_hbuf_filled_slots()
484 	write_ptr = (char) ((hcsr & H_CBWP) >> 16);  in mei_hbuf_filled_slots()
1149 	u32 hcsr;  in mei_me_hw_reset()  local
1162 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1168 	if ((hcsr & H_RST) == H_RST) {  in mei_me_hw_reset()
1169 		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);  in mei_me_hw_reset()
1170 		hcsr &= ~H_RST;  in mei_me_hw_reset()
1171 		mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset()
1172 		hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1175 	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;  in mei_me_hw_reset()
1178 		hcsr &= ~H_CSR_IE_MASK;  in mei_me_hw_reset()
1181 	mei_hcsr_write(dev, hcsr);  in mei_me_hw_reset()
1187 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1189 	if ((hcsr & H_RST) == 0)  in mei_me_hw_reset()
1190 		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);  in mei_me_hw_reset()
1192 	if ((hcsr & H_RDY) == H_RDY)  in mei_me_hw_reset()
1193 		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);  in mei_me_hw_reset()
1217 	u32 hcsr;  in mei_me_irq_quick_handler()  local
1219 	hcsr = mei_hcsr_read(dev);  in mei_me_irq_quick_handler()
1220 	if (!me_intr_src(hcsr))  in mei_me_irq_quick_handler()
1223 	dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));  in mei_me_irq_quick_handler()
1226 	me_intr_disable(dev, hcsr);  in mei_me_irq_quick_handler()
1245 	u32 hcsr;  in mei_me_irq_thread_handler()  local
1252 	hcsr = mei_hcsr_read(dev);  in mei_me_irq_thread_handler()
1253 	me_intr_clear(dev, hcsr);  in mei_me_irq_thread_handler()
1267 	mei_me_pg_intr(dev, me_intr_src(hcsr));  in mei_me_irq_thread_handler()