Lines Matching +full:host +full:- +full:only

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
53 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
108 /* Host Firmware Status Registers in PCI Config Space */
122 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
124 /* H_CSR - Host Control Status register */
126 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
128 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
130 /* H_HGC_CSR - PGI register */
132 /* H_D0I3C - D0I3 Control  */
135 /* register bits of H_CSR (Host Control Status register) */
136 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
138 /* Host Circular Buffer Write Pointer */
140 /* Host Circular Buffer Read Pointer */
142 /* Host Reset */
144 /* Host Ready */
146 /* Host Interrupt Generate */
148 /* Host Interrupt Status */
150 /* Host Interrupt Enable */
152 /* Host D0I3 Interrupt Enable */
154 /* Host D0I3 Interrupt Status */
161 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
162 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
165 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
167 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
169 /* ME Power Gate Isolation Capability HRA  - host ready only access */
171 /* ME Reset HRA - host read only access to ME_RST */
173 /* ME Ready HRA - host read only access to ME_RDY */
175 /* ME Interrupt Generate HRA - host read only access to ME_IG */
177 /* ME Interrupt Status HRA - host read only access to ME_IS */
179 /* ME Interrupt Enable HRA - host read only access to ME_IE */