Lines Matching +full:0 +full:xf
15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
31 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
32 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
35 (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
36 (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
37 (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
40 (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
41 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
42 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
45 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
46 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
47 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
48 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
51 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
52 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
53 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
54 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
57 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
58 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
59 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
62 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
63 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
64 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)))
67 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
68 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
69 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
72 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
73 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
74 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
77 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
78 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
79 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
82 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
83 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
84 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
87 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
88 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
89 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
92 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
93 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
94 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
96 #define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
99 #define CFG_RST_L_PSOC_MASK BIT_MASK(0)
136 #define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
170 #define UNIT_RST_L_PSOC_SHIFT 0
203 #define UNIT_RST_H_MME_3_SHIFT 0
263 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
264 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3
266 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30
268 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100
270 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000
272 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000
274 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000
300 #define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
301 #define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
302 #define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000
336 #define RAZWI_INITIATOR_AXI_ID_MASK 0xF
338 #define RAZWI_INITIATOR_X_MASK 0xF
340 #define RAZWI_INITIATOR_Y_MASK 0x7
359 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)
361 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)
363 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)
365 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)
379 #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
380 #define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
382 #define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
384 #define MME_ACC_ACC_STALL_R_SHIFT 0
385 #define MME_SBAB_SB_STALL_R_SHIFT 0
387 #define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700
388 #define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000
390 #define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0
391 #define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0
394 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0
395 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1
397 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2
399 #define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0
400 #define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0
401 #define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0
402 #define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0
404 #define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0
405 #define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0
407 #define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0
408 #define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0
411 #define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
412 #define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
415 #define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
416 #define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
418 #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
419 #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
420 #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
426 #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
427 #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2