Lines Matching refs:CFG_BASE
467 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; in gaudi_get_fixed_properties()
493 (CFG_BASE - SPI_FLASH_BASE_ADDR); in gaudi_pci_bars_map()
1841 mtr_base_en_lo = lower_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1843 mtr_base_en_hi = upper_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1845 so_base_en_lo = lower_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1847 so_base_en_hi = upper_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1849 mtr_base_ws_lo = lower_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1851 mtr_base_ws_hi = upper_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1853 so_base_ws_lo = lower_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1855 so_base_ws_hi = upper_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1895 lower_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1898 upper_32_bits(CFG_BASE + in gaudi_init_pci_dma_qman()
1936 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_dma_core()
1938 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_dma_core()
2008 mtr_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2010 mtr_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2012 so_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2014 so_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2052 lower_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2055 upper_32_bits(CFG_BASE + in gaudi_init_hbm_dma_qman()
2124 mtr_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2126 mtr_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2128 so_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2130 so_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2170 lower_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2173 upper_32_bits(CFG_BASE + in gaudi_init_mme_qman()
2244 mtr_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2246 mtr_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2248 so_base_lo = lower_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2250 so_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2291 lower_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2294 upper_32_bits(CFG_BASE + in gaudi_init_tpc_qman()
2331 so_base_hi = upper_32_bits(CFG_BASE + in gaudi_init_tpc_qmans()
2634 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in gaudi_enable_timestamp()
2637 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); in gaudi_enable_timestamp()
2638 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); in gaudi_enable_timestamp()
2641 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); in gaudi_enable_timestamp()
2647 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in gaudi_disable_timestamp()
4319 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_MSI_INTR_0 + msi_vec * 4); in gaudi_add_end_of_cb_packets()
4440 u64 sob_addr = CFG_BASE + in gaudi_restore_dma_registers()
4535 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { in gaudi_debugfs_read32()
4545 *val = RREG32(addr - CFG_BASE); in gaudi_debugfs_read32()
4582 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { in gaudi_debugfs_write32()
4592 WREG32(addr - CFG_BASE, val); in gaudi_debugfs_write32()
4629 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { in gaudi_debugfs_read64()
4639 u32 val_l = RREG32(addr - CFG_BASE); in gaudi_debugfs_read64()
4640 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE); in gaudi_debugfs_read64()
4680 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { in gaudi_debugfs_write64()
4690 WREG32(addr - CFG_BASE, lower_32_bits(val)); in gaudi_debugfs_write64()
4691 WREG32(addr + sizeof(u32) - CFG_BASE, in gaudi_debugfs_write64()
5254 if (params->block_address >= CFG_BASE) in gaudi_extract_ecc_info()
5255 params->block_address -= CFG_BASE; in gaudi_extract_ecc_info()
6275 lower_32_bits(CFG_BASE + in gaudi_run_tpc_kernel()
6524 fence_addr += CFG_BASE; in gaudi_gen_wait_cb()