Lines Matching defs:asic_fixed_properties
326 struct asic_fixed_properties { struct
327 struct hw_queue_properties *hw_queues_props;
328 struct cpucp_info cpucp_info;
329 char uboot_ver[VERSION_MAX_LEN];
330 char preboot_ver[VERSION_MAX_LEN];
331 struct hl_mmu_properties dmmu;
332 struct hl_mmu_properties pmmu;
333 struct hl_mmu_properties pmmu_huge;
334 u64 sram_base_address;
335 u64 sram_end_address;
336 u64 sram_user_base_address;
337 u64 dram_base_address;
338 u64 dram_end_address;
339 u64 dram_user_base_address;
340 u64 dram_size;
341 u64 dram_pci_bar_size;
342 u64 max_power_default;
343 u64 dram_size_for_default_page_mapping;
344 u64 pcie_dbi_base_address;
345 u64 pcie_aux_dbi_reg_addr;
346 u64 mmu_pgt_addr;
347 u64 mmu_dram_default_page_addr;
348 u64 cb_va_start_addr;
349 u64 cb_va_end_addr;
350 u32 mmu_pgt_size;
351 u32 mmu_pte_size;
352 u32 mmu_hop_table_size;
353 u32 mmu_hop0_tables_total_size;
354 u32 dram_page_size;
355 u32 cfg_size;
356 u32 sram_size;
357 u32 max_asid;
358 u32 num_of_events;
359 u32 psoc_pci_pll_nr;
360 u32 psoc_pci_pll_nf;
361 u32 psoc_pci_pll_od;
362 u32 psoc_pci_pll_div_factor;
363 u32 psoc_timestamp_frequency;
364 u32 high_pll;
365 u32 cb_pool_cb_cnt;
366 u32 cb_pool_cb_size;
367 u32 max_pending_cs;
368 u32 max_queues;
369 u16 sync_stream_first_sob;
370 u16 sync_stream_first_mon;
371 u16 first_available_user_sob[HL_MAX_DCORES];
372 u16 first_available_user_mon[HL_MAX_DCORES];
373 u8 tpc_enabled_mask;
374 u8 completion_queues_count;
375 u8 fw_security_disabled;