475 struct cxl_afu {  struct
476 	struct cxl_afu_native *native;  argument
477 	struct cxl_afu_guest *guest;  argument
478 	irq_hw_number_t serr_hwirq;
479 	unsigned int serr_virq;
480 	char *psl_irq_name;
481 	char *err_irq_name;
482 	void __iomem *p2n_mmio;
483 	phys_addr_t psn_phys;
484 	u64 pp_size;
486 	struct cxl *adapter;
487 	struct device dev;
488 	struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
489 	struct device *chardev_s, *chardev_m, *chardev_d;
490 	struct idr contexts_idr;
491 	struct dentry *debugfs;
492 	struct mutex contexts_lock;
493 	spinlock_t afu_cntl_lock;
496 	atomic_t configured_state;
499 	u64 eb_len, eb_offset;
500 	struct bin_attribute attr_eb;
503 	struct pci_controller *phb;
505 	int pp_irqs;
506 	int irqs_max;
507 	int num_procs;
508 	int max_procs_virtualised;
509 	int slice;
510 	int modes_supported;
511 	int current_mode;
512 	int crs_num;
513 	u64 crs_len;
514 	u64 crs_offset;
515 	struct list_head crs;
539 	struct cxl_afu *afu;  argument