297 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,  in rtsx_pci_add_cmd()  function
318 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
545 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
559 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
588 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
602 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
621 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_set_pull_ctl()
777 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in rtsx_pci_switch_clock()
779 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,  in rtsx_pci_switch_clock()
781 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rtsx_pci_switch_clock()
782 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,  in rtsx_pci_switch_clock()
784 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rtsx_pci_switch_clock()
785 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);  in rtsx_pci_switch_clock()
787 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
789 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
1296 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);  in rtsx_pci_init_hw()
1298 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);  in rtsx_pci_init_hw()
1300 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);  in rtsx_pci_init_hw()
1302 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);  in rtsx_pci_init_hw()
1304 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,  in rtsx_pci_init_hw()
1307 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,  in rtsx_pci_init_hw()
1310 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1313 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1316 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);  in rtsx_pci_init_hw()
1319 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);  in rtsx_pci_init_hw()
1321 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in rtsx_pci_init_hw()
1326 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);  in rtsx_pci_init_hw()
1331 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);  in rtsx_pci_init_hw()
1337 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);  in rtsx_pci_init_hw()