30 		{0x13, 0x13, 0x13},  in rts5228_fill_driving()
31 		{0x96, 0x96, 0x96},  in rts5228_fill_driving()
32 		{0x7F, 0x7F, 0x7F},  in rts5228_fill_driving()
33 		{0x96, 0x96, 0x96},  in rts5228_fill_driving()
36 		{0x99, 0x99, 0x99},  in rts5228_fill_driving()
37 		{0xB5, 0xB5, 0xB5},  in rts5228_fill_driving()
38 		{0xE6, 0x7E, 0xFE},  in rts5228_fill_driving()
39 		{0x6B, 0x6B, 0x6B},  in rts5228_fill_driving()
52 			 0xFF, driving[drive_sel][0]);  in rts5228_fill_driving()
55 			 0xFF, driving[drive_sel][1]);  in rts5228_fill_driving()
58 			 0xFF, driving[drive_sel][2]);  in rts5228_fill_driving()
66 	/* 0x724~0x727 */  in rtsx5228_fetch_vendor_settings()
68 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);  in rtsx5228_fetch_vendor_settings()
77 	/* 0x814~0x817 */  in rtsx5228_fetch_vendor_settings()
79 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);  in rtsx5228_fetch_vendor_settings()
91 	return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);  in rts5228_optimize_phy()
96 	/* Set relink_time to 0 */  in rts5228_force_power_down()
97 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);  in rts5228_force_power_down()
98 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);  in rts5228_force_power_down()
100 				RELINK_TIME_MASK, 0);  in rts5228_force_power_down()
124 		0x02, 0x02);  in rts5228_turn_on_led()
130 		0x02, 0x00);  in rts5228_turn_off_led()
134  *     SD_DAT[3:0] ==> pull up
141 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
142 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
143 	0,
147  *     SD_DAT[3:0] ==> pull down
154 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
155 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
156 	0,
164 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,  in rts5228_sd_set_sample_push_timing_sd30()
166 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5228_sd_set_sample_push_timing_sd30()
168 	return 0;  in rts5228_sd_set_sample_push_timing_sd30()
199 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,  in rts5228_card_power_on()
203 			0xFF, SD20_RX_POS_EDGE);  in rts5228_card_power_on()
204 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);  in rts5228_card_power_on()
209 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);  in rts5228_card_power_on()
212 			SD30_CLK_STOP_CFG0, 0);  in rts5228_card_power_on()
218 	return 0;  in rts5228_card_power_on()
224 	u16 val = 0;  in rts5228_switch_output_voltage()
234 		if (err < 0)  in rts5228_switch_output_voltage()
240 				SD_IO_USING_1V8, 0);  in rts5228_switch_output_voltage()
246 		if (err < 0)  in rts5228_switch_output_voltage()
261 	return 0;  in rts5228_switch_output_voltage()
282 	u8 val = 0;  in rts5228_enable_ocp()
285 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);  in rts5228_enable_ocp()
293 	u8 mask = 0;  in rts5228_disable_ocp()
296 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5228_disable_ocp()
298 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);  in rts5228_disable_ocp()
303 	int err = 0;  in rts5228_card_power_off()
307 				RTS5228_LDO_POWERON_MASK, 0);  in rts5228_card_power_off()
308 	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);  in rts5228_card_power_off()
344 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);  in rts5228_init_ocp()
350 	u8 mask = 0;  in rts5228_clear_ocpstat()
351 	u8 val = 0;  in rts5228_clear_ocpstat()
359 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5228_clear_ocpstat()
373 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);  in rts5228_process_ocp()
374 		pcr->ocp_stat = 0;  in rts5228_process_ocp()
392 	if (0 == (lval & 0x0F))  in rts5228_init_from_cfg()
417 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);  in rts5228_init_from_cfg()
449 	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);  in rts5228_extra_init_hw()
461 	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);  in rts5228_extra_init_hw()
467 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);  in rts5228_extra_init_hw()
469 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);  in rts5228_extra_init_hw()
482 	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);  in rts5228_extra_init_hw()
483 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);  in rts5228_extra_init_hw()
487 	return 0;  in rts5228_extra_init_hw()
499 	val |= (pcr->aspm_en & 0x02);  in rts5228_enable_aspm()
514 					   PCI_EXP_LNKCTL_ASPMC, 0);  in rts5228_disable_aspm()
518 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);  in rts5228_disable_aspm()
535 	u8 val = 0;  in rts5228_set_l1off_cfg_sub_d0()
603 	if (err < 0)  in rts5228_pci_switch_clock()
616 		return 0;  in rts5228_pci_switch_clock()
667 		ssc_depth = 0;  in rts5228_pci_switch_clock()
675 			0xFF, (div << 4) | mcu_cnt);  in rts5228_pci_switch_clock()
676 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rts5228_pci_switch_clock()
679 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rts5228_pci_switch_clock()
683 				PHASE_NOT_RESET, 0);  in rts5228_pci_switch_clock()
685 				PHASE_NOT_RESET, 0);  in rts5228_pci_switch_clock()
693 	if (err < 0)  in rts5228_pci_switch_clock()
698 	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5228_pci_switch_clock()
699 	if (err < 0)  in rts5228_pci_switch_clock()
703 	return 0;  in rts5228_pci_switch_clock()
716 	pcr->flags = 0;  in rts5228_init_params()
739 	option->ltr_l1off_sspwrgate = 0x7F;  in rts5228_init_params()
740 	option->ltr_l1off_snooze_sspwrgate = 0x78;  in rts5228_init_params()