49 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,  in rts5227_fill_driving()
51 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,  in rts5227_fill_driving()
53 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,  in rts5227_fill_driving()
152 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);  in rts5227_extra_init_hw()
154 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);  in rts5227_extra_init_hw()
156 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);  in rts5227_extra_init_hw()
157 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);  in rts5227_extra_init_hw()
159 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);  in rts5227_extra_init_hw()
163 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);  in rts5227_extra_init_hw()
165 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);  in rts5227_extra_init_hw()
170 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);  in rts5227_extra_init_hw()
172 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);  in rts5227_extra_init_hw()
175 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,  in rts5227_extra_init_hw()
178 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,  in rts5227_extra_init_hw()
181 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);  in rts5227_extra_init_hw()
226 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rts5227_card_power_on()
229 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rts5227_card_power_on()
239 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rts5227_card_power_on()
242 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rts5227_card_power_on()
245 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,  in rts5227_card_power_on()
247 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,  in rts5227_card_power_on()