Lines Matching full:r2
54 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
58 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
61 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
64 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
67 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
70 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
73 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
76 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
79 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
82 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
85 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
88 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
91 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
94 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
97 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
104 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
107 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
110 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
113 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
116 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
119 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
123 add r4, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
146 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
149 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
153 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
157 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
161 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
165 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
169 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
172 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
175 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
178 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
181 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
184 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
187 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
194 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
197 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
200 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
203 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
206 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
209 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
212 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
220 add r3, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
236 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
240 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
241 and r2, r1, #SDRAM_TYPE_MASK
242 cmp r2, #EMIF_SDCFG_TYPE_DDR2
260 ldr r2, [r0, #EMIF_SDRAM_CONFIG]
261 and r2, r2, #SDRAM_TYPE_MASK
262 cmp r2, #EMIF_SDCFG_TYPE_DDR3
274 mov r2, #0x2000
276 subs r2, r2, #0x1
300 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
320 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
330 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
357 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
359 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]