Lines Matching full:r1
57 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
58 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
60 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
61 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
63 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
64 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
66 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
67 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
69 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
70 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
72 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
73 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
75 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
76 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
78 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
79 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
81 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
82 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
84 ldr r1, [r0, #EMIF_COS_CONFIG]
85 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
87 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
88 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
90 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
91 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
93 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
94 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
96 ldr r1, [r0, #EMIF_OCP_CONFIG]
97 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
103 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
104 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
106 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
107 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
109 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
110 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
112 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
113 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
115 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
116 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
118 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
119 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
126 ldr r1, [r3, r5]
127 str r1, [r4, r5]
149 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
150 str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
151 str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
153 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
154 str r1, [r0, #EMIF_SDRAM_TIMING_1]
155 str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
157 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
158 str r1, [r0, #EMIF_SDRAM_TIMING_2]
159 str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
161 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
162 str r1, [r0, #EMIF_SDRAM_TIMING_3]
163 str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
165 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
166 str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
167 str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
169 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
170 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
172 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
173 str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
175 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
176 str r1, [r0, #EMIF_COS_CONFIG]
178 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
179 str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
181 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
182 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
184 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
185 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
187 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
188 str r1, [r0, #EMIF_OCP_CONFIG]
194 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
195 str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
197 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
198 str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
200 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
201 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
203 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
204 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
206 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
207 str r1, [r0, #EMIF_DLL_CALIB_CTRL]
209 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
210 str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
212 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
213 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
223 ldr r1, [r3, r5]
224 str r1, [r4, r5]
236 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
237 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
240 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
241 and r2, r1, #SDRAM_TYPE_MASK
243 streq r1, [r0, #EMIF_SDRAM_CONFIG]
280 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
281 tst r1, #RDWRLVLFULL_START
302 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
303 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
304 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
305 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
330 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
331 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
332 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
333 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
334 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
335 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
338 1: ldr r1, [r0, #EMIF_STATUS]
339 tst r1, #EMIF_STATUS_READY
359 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
360 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
361 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
364 1: ldr r1, [r0, #EMIF_STATUS]
365 tst r1, #EMIF_STATUS_READY