Lines Matching +full:max +full:- +full:bit +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0
76 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
77 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
78 #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
80 #define EMC_TIMING_UPDATE BIT(0)
82 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
83 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
85 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
87 #define EMC_DBG_FORCE_UPDATE BIT(2)
88 #define EMC_DBG_READ_DQM_CTRL BIT(9)
89 #define EMC_DBG_CFG_PRIORITY BIT(24)
141 unsigned long rate; member
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
183 unsigned long rate) in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
190 timing = &emc->timings[i]; in tegra_emc_find_timing()
196 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
203 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
205 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change()
209 return -EINVAL; in emc_prepare_timing_change()
211 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
212 __func__, timing->rate, rate); in emc_prepare_timing_change()
215 for (i = 0; i < ARRAY_SIZE(timing->data); i++) in emc_prepare_timing_change()
216 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
217 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
220 readl_relaxed(emc->regs + emc_timing_registers[i - 1]); in emc_prepare_timing_change()
230 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); in emc_complete_timing_change()
235 emc->regs + EMC_TIMING_CONTROL); in emc_complete_timing_change()
239 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
243 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
259 err = emc_prepare_timing_change(emc, cnd->new_rate); in tegra_emc_clk_change_notify()
263 err = emc_prepare_timing_change(emc, cnd->old_rate); in tegra_emc_clk_change_notify()
285 u32 rate; in load_one_timing_from_dt() local
288 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { in load_one_timing_from_dt()
289 dev_err(emc->dev, "incompatible DT node: %pOF\n", node); in load_one_timing_from_dt()
290 return -EINVAL; in load_one_timing_from_dt()
293 err = of_property_read_u32(node, "clock-frequency", &rate); in load_one_timing_from_dt()
295 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
300 err = of_property_read_u32_array(node, "nvidia,emc-registers", in load_one_timing_from_dt()
301 timing->data, in load_one_timing_from_dt()
304 dev_err(emc->dev, in load_one_timing_from_dt()
311 * The EMC clock rate is twice the bus rate, and the bus rate is in load_one_timing_from_dt()
314 timing->rate = rate * 2 * 1000; in load_one_timing_from_dt()
316 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", in load_one_timing_from_dt()
317 __func__, node, timing->rate); in load_one_timing_from_dt()
327 if (a->rate < b->rate) in cmp_timings()
328 return -1; in cmp_timings()
330 if (a->rate > b->rate) in cmp_timings()
346 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); in tegra_emc_load_timings_from_dt()
347 return -EINVAL; in tegra_emc_load_timings_from_dt()
350 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
352 if (!emc->timings) in tegra_emc_load_timings_from_dt()
353 return -ENOMEM; in tegra_emc_load_timings_from_dt()
355 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
356 timing = emc->timings; in tegra_emc_load_timings_from_dt()
366 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
369 dev_info(emc->dev, in tegra_emc_load_timings_from_dt()
370 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", in tegra_emc_load_timings_from_dt()
371 emc->num_timings, in tegra_emc_load_timings_from_dt()
373 emc->timings[0].rate / 1000000, in tegra_emc_load_timings_from_dt()
374 emc->timings[emc->num_timings - 1].rate / 1000000); in tegra_emc_load_timings_from_dt()
386 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) in tegra_emc_find_node_by_ram_code()
387 return of_node_get(dev->of_node); in tegra_emc_find_node_by_ram_code()
391 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; in tegra_emc_find_node_by_ram_code()
392 np = of_find_node_by_name(np, "emc-tables")) { in tegra_emc_find_node_by_ram_code()
393 err = of_property_read_u32(np, "nvidia,ram-code", &value); in tegra_emc_find_node_by_ram_code()
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
416 * Depending on a memory type, DRAM should enter either self-refresh in emc_setup_hw()
417 * or power-down state on EMC clock change. in emc_setup_hw()
421 dev_err(emc->dev, in emc_setup_hw()
422 "bootloader didn't specify DRAM auto-suspend mode\n"); in emc_setup_hw()
423 return -EINVAL; in emc_setup_hw()
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
431 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
432 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
435 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
440 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
445 static long emc_round_rate(unsigned long rate, in emc_round_rate() argument
454 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
456 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
457 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
460 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
461 i = max(i, 1u) - 1; in emc_round_rate()
463 if (emc->timings[i].rate < min_rate) in emc_round_rate()
467 if (emc->timings[i].rate < min_rate) in emc_round_rate()
470 timing = &emc->timings[i]; in emc_round_rate()
475 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
476 rate, min_rate, max_rate); in emc_round_rate()
477 return -EINVAL; in emc_round_rate()
480 return timing->rate; in emc_round_rate()
487 * to control the EMC frequency. The top-level directory can be found here:
493 * - available_rates: This file contains a list of valid, space-separated
496 * - min_rate: Writing a value to this file sets the given frequency as the
501 * - max_rate: Similarily to the min_rate file, writing a value to this file
508 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
512 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
513 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
521 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show()
525 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
526 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
539 inode->i_private); in tegra_emc_debug_available_rates_open()
549 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) in tegra_emc_debug_min_rate_get() argument
553 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
558 static int tegra_emc_debug_min_rate_set(void *data, u64 rate) in tegra_emc_debug_min_rate_set() argument
563 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
564 return -EINVAL; in tegra_emc_debug_min_rate_set()
566 err = clk_set_min_rate(emc->clk, rate); in tegra_emc_debug_min_rate_set()
570 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
579 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) in tegra_emc_debug_max_rate_get() argument
583 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
588 static int tegra_emc_debug_max_rate_set(void *data, u64 rate) in tegra_emc_debug_max_rate_set() argument
593 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
594 return -EINVAL; in tegra_emc_debug_max_rate_set()
596 err = clk_set_max_rate(emc->clk, rate); in tegra_emc_debug_max_rate_set()
600 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
611 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
615 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
616 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
618 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
619 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
620 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
622 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
623 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
626 if (!emc->num_timings) { in tegra_emc_debugfs_init()
627 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
628 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
631 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
632 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
634 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
635 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
636 emc->clk); in tegra_emc_debugfs_init()
639 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
640 if (!emc->debugfs.root) { in tegra_emc_debugfs_init()
641 dev_err(emc->dev, "failed to create debugfs directory\n"); in tegra_emc_debugfs_init()
645 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
647 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
649 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
661 if (of_get_child_count(pdev->dev.of_node) == 0) { in tegra_emc_probe()
662 dev_info(&pdev->dev, in tegra_emc_probe()
669 dev_err(&pdev->dev, "interrupt not specified\n"); in tegra_emc_probe()
670 dev_err(&pdev->dev, "please update your device tree\n"); in tegra_emc_probe()
674 np = tegra_emc_find_node_by_ram_code(&pdev->dev); in tegra_emc_probe()
676 return -EINVAL; in tegra_emc_probe()
678 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
681 return -ENOMEM; in tegra_emc_probe()
684 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; in tegra_emc_probe()
685 emc->dev = &pdev->dev; in tegra_emc_probe()
693 emc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_emc_probe()
694 if (IS_ERR(emc->regs)) in tegra_emc_probe()
695 return PTR_ERR(emc->regs); in tegra_emc_probe()
701 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, in tegra_emc_probe()
702 dev_name(&pdev->dev), emc); in tegra_emc_probe()
704 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); in tegra_emc_probe()
710 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra_emc_probe()
711 if (IS_ERR(emc->clk)) { in tegra_emc_probe()
712 err = PTR_ERR(emc->clk); in tegra_emc_probe()
713 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); in tegra_emc_probe()
717 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_probe()
719 dev_err(&pdev->dev, "failed to register clk notifier: %d\n", in tegra_emc_probe()
736 { .compatible = "nvidia,tegra20-emc", },
743 .name = "tegra20-emc",