Lines Matching full:timing
486 /* Timing change sequence functions */
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
547 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
552 timing = &emc->timings[i]; in tegra_emc_find_timing()
557 if (!timing) { in tegra_emc_find_timing()
558 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
562 return timing; in tegra_emc_find_timing()
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
576 if (!timing) in tegra_emc_prepare_timing_change()
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
581 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
613 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
633 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
639 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
658 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
660 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
666 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
667 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
670 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
673 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
679 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
680 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
683 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
684 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
687 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
688 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
698 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
702 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
708 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
716 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
722 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
745 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
746 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
747 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
750 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
752 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
762 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
763 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
764 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
766 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
767 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
771 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
796 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change() local
800 if (!timing) in tegra_emc_complete_timing_change()
807 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
808 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
816 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
820 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
822 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
829 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
830 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
834 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
838 /* Wait for timing to settle */ in tegra_emc_complete_timing_change()
842 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
845 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
851 struct emc_timing *timing) in emc_read_current_timing() argument
856 timing->emc_burst_data[i] = in emc_read_current_timing()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
861 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
862 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
863 timing->emc_mode_1 = 0; in emc_read_current_timing()
864 timing->emc_mode_2 = 0; in emc_read_current_timing()
865 timing->emc_mode_4 = 0; in emc_read_current_timing()
866 timing->emc_mode_reset = 0; in emc_read_current_timing()
883 struct emc_timing *timing, in load_one_timing_from_dt() argument
891 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", in load_one_timing_from_dt()
896 timing->rate = value; in load_one_timing_from_dt()
899 timing->emc_burst_data, in load_one_timing_from_dt()
900 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
903 "timing %pOFn: failed to read emc burst data: %d\n", in load_one_timing_from_dt()
909 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
911 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
958 struct emc_timing *timing; in tegra_emc_load_timings_from_dt() local
962 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
970 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
972 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
979 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()