53 	value = mc_readl(mc, rst->control) | BIT(rst->bit);  in tegra_mc_block_dma_common()
64 	return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;  in tegra_mc_dma_idling_common()
75 	value = mc_readl(mc, rst->control) & ~BIT(rst->bit);  in tegra_mc_unblock_dma_common()
86 	return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;  in tegra_mc_reset_status_common()
256 	value = mc_readl(mc, MC_EMEM_ARB_CFG);  in tegra_mc_setup_latency_allowance()
266 		value = mc_readl(mc, la->reg);  in tegra_mc_setup_latency_allowance()
306 	dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);  in tegra_mc_get_emem_device_count()
431 	status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;  in tegra_mc_irq()
445 		value = mc_readl(mc, MC_ERR_STATUS);  in tegra_mc_irq()
507 		value = mc_readl(mc, MC_ERR_ADR);  in tegra_mc_irq()
528 	status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;  in tegra20_mc_irq()
543 			value = mc_readl(mc, reg);  in tegra20_mc_irq()
554 			value = mc_readl(mc, reg);  in tegra20_mc_irq()
565 			value = mc_readl(mc, reg);  in tegra20_mc_irq()
581 		addr = mc_readl(mc, reg + sizeof(u32));  in tegra20_mc_irq()