Lines Matching +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
51 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
53 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
54 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
56 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_block_dma_common()
64 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
73 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_unblock_dma_common()
75 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
76 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
78 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_unblock_dma_common()
86 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
106 for (i = 0; i < mc->soc->num_resets; i++) in tegra_mc_reset_find()
107 if (mc->soc->resets[i].id == id) in tegra_mc_reset_find()
108 return &mc->soc->resets[i]; in tegra_mc_reset_find()
124 return -ENODEV; in tegra_mc_hotreset_assert()
126 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_assert()
128 return -ENODEV; in tegra_mc_hotreset_assert()
130 if (rst_ops->block_dma) { in tegra_mc_hotreset_assert()
132 err = rst_ops->block_dma(mc, rst); in tegra_mc_hotreset_assert()
134 dev_err(mc->dev, "failed to block %s DMA: %d\n", in tegra_mc_hotreset_assert()
135 rst->name, err); in tegra_mc_hotreset_assert()
140 if (rst_ops->dma_idling) { in tegra_mc_hotreset_assert()
142 while (!rst_ops->dma_idling(mc, rst)) { in tegra_mc_hotreset_assert()
143 if (!retries--) { in tegra_mc_hotreset_assert()
144 dev_err(mc->dev, "failed to flush %s DMA\n", in tegra_mc_hotreset_assert()
145 rst->name); in tegra_mc_hotreset_assert()
146 return -EBUSY; in tegra_mc_hotreset_assert()
153 if (rst_ops->hotreset_assert) { in tegra_mc_hotreset_assert()
155 err = rst_ops->hotreset_assert(mc, rst); in tegra_mc_hotreset_assert()
157 dev_err(mc->dev, "failed to hot reset %s: %d\n", in tegra_mc_hotreset_assert()
158 rst->name, err); in tegra_mc_hotreset_assert()
176 return -ENODEV; in tegra_mc_hotreset_deassert()
178 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_deassert()
180 return -ENODEV; in tegra_mc_hotreset_deassert()
182 if (rst_ops->hotreset_deassert) { in tegra_mc_hotreset_deassert()
184 err = rst_ops->hotreset_deassert(mc, rst); in tegra_mc_hotreset_deassert()
186 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", in tegra_mc_hotreset_deassert()
187 rst->name, err); in tegra_mc_hotreset_deassert()
192 if (rst_ops->unblock_dma) { in tegra_mc_hotreset_deassert()
194 err = rst_ops->unblock_dma(mc, rst); in tegra_mc_hotreset_deassert()
196 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", in tegra_mc_hotreset_deassert()
197 rst->name, err); in tegra_mc_hotreset_deassert()
214 return -ENODEV; in tegra_mc_hotreset_status()
216 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_status()
218 return -ENODEV; in tegra_mc_hotreset_status()
220 return rst_ops->reset_status(mc, rst); in tegra_mc_hotreset_status()
233 mc->reset.ops = &tegra_mc_reset_ops; in tegra_mc_reset_setup()
234 mc->reset.owner = THIS_MODULE; in tegra_mc_reset_setup()
235 mc->reset.of_node = mc->dev->of_node; in tegra_mc_reset_setup()
236 mc->reset.of_reset_n_cells = 1; in tegra_mc_reset_setup()
237 mc->reset.nr_resets = mc->soc->num_resets; in tegra_mc_reset_setup()
239 err = reset_controller_register(&mc->reset); in tegra_mc_reset_setup()
253 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); in tegra_mc_setup_latency_allowance()
262 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_setup_latency_allowance()
263 const struct tegra_mc_la *la = &mc->soc->clients[i].la; in tegra_mc_setup_latency_allowance()
266 value = mc_readl(mc, la->reg); in tegra_mc_setup_latency_allowance()
267 value &= ~(la->mask << la->shift); in tegra_mc_setup_latency_allowance()
268 value |= (la->def & la->mask) << la->shift; in tegra_mc_setup_latency_allowance()
269 mc_writel(mc, value, la->reg); in tegra_mc_setup_latency_allowance()
283 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
284 if (mc->timings[i].rate == rate) { in tegra_mc_write_emem_configuration()
285 timing = &mc->timings[i]; in tegra_mc_write_emem_configuration()
291 dev_err(mc->dev, "no memory timing registered for rate %lu\n", in tegra_mc_write_emem_configuration()
293 return -EINVAL; in tegra_mc_write_emem_configuration()
296 for (i = 0; i < mc->soc->num_emem_regs; ++i) in tegra_mc_write_emem_configuration()
297 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
320 err = of_property_read_u32(node, "clock-frequency", &tmp); in load_one_timing()
322 dev_err(mc->dev, in load_one_timing()
327 timing->rate = tmp; in load_one_timing()
328 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, in load_one_timing()
330 if (!timing->emem_data) in load_one_timing()
331 return -ENOMEM; in load_one_timing()
333 err = of_property_read_u32_array(node, "nvidia,emem-configuration", in load_one_timing()
334 timing->emem_data, in load_one_timing()
335 mc->soc->num_emem_regs); in load_one_timing()
337 dev_err(mc->dev, in load_one_timing()
353 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), in load_timings()
355 if (!mc->timings) in load_timings()
356 return -ENOMEM; in load_timings()
358 mc->num_timings = child_count; in load_timings()
361 timing = &mc->timings[i++]; in load_timings()
381 mc->num_timings = 0; in tegra_mc_setup_timings()
383 for_each_child_of_node(mc->dev->of_node, node) { in tegra_mc_setup_timings()
384 err = of_property_read_u32(node, "nvidia,ram-code", in tegra_mc_setup_timings()
396 if (mc->num_timings == 0) in tegra_mc_setup_timings()
397 dev_warn(mc->dev, in tegra_mc_setup_timings()
421 [6] = "SMMU translation error",
431 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra_mc_irq()
448 if (mc->soc->num_address_bits > 32) { in tegra_mc_irq()
465 id = value & mc->soc->client_id_mask; in tegra_mc_irq()
467 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_irq()
468 if (mc->soc->clients[i].id == id) { in tegra_mc_irq()
469 client = mc->soc->clients[i].name; in tegra_mc_irq()
486 perm[2] = '-'; in tegra_mc_irq()
491 perm[3] = '-'; in tegra_mc_irq()
494 perm[4] = '-'; in tegra_mc_irq()
510 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", in tegra_mc_irq()
528 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_irq()
545 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
556 id = (value >> 1) & mc->soc->client_id_mask; in tegra20_mc_irq()
567 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
580 client = mc->soc->clients[id].name; in tegra20_mc_irq()
583 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", in tegra20_mc_irq()
602 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); in tegra_mc_probe()
604 return -ENOMEM; in tegra_mc_probe()
607 spin_lock_init(&mc->lock); in tegra_mc_probe()
608 mc->soc = of_device_get_match_data(&pdev->dev); in tegra_mc_probe()
609 mc->dev = &pdev->dev; in tegra_mc_probe()
611 mask = DMA_BIT_MASK(mc->soc->num_address_bits); in tegra_mc_probe()
613 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); in tegra_mc_probe()
615 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); in tegra_mc_probe()
620 mc->tick = 30; in tegra_mc_probe()
623 mc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_mc_probe()
624 if (IS_ERR(mc->regs)) in tegra_mc_probe()
625 return PTR_ERR(mc->regs); in tegra_mc_probe()
627 mc->clk = devm_clk_get(&pdev->dev, "mc"); in tegra_mc_probe()
628 if (IS_ERR(mc->clk)) { in tegra_mc_probe()
629 dev_err(&pdev->dev, "failed to get MC clock: %ld\n", in tegra_mc_probe()
630 PTR_ERR(mc->clk)); in tegra_mc_probe()
631 return PTR_ERR(mc->clk); in tegra_mc_probe()
635 if (mc->soc == &tegra20_mc_soc) { in tegra_mc_probe()
645 dev_err(&pdev->dev, in tegra_mc_probe()
655 dev_err(&pdev->dev, "failed to setup timings: %d\n", in tegra_mc_probe()
661 mc->irq = platform_get_irq(pdev, 0); in tegra_mc_probe()
662 if (mc->irq < 0) { in tegra_mc_probe()
663 dev_err(&pdev->dev, "interrupt not specified\n"); in tegra_mc_probe()
664 return mc->irq; in tegra_mc_probe()
667 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); in tegra_mc_probe()
669 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
671 err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, in tegra_mc_probe()
672 dev_name(&pdev->dev), mc); in tegra_mc_probe()
674 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, in tegra_mc_probe()
681 dev_err(&pdev->dev, "failed to register reset controller: %d\n", in tegra_mc_probe()
684 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { in tegra_mc_probe()
685 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); in tegra_mc_probe()
686 if (IS_ERR(mc->smmu)) { in tegra_mc_probe()
687 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", in tegra_mc_probe()
688 PTR_ERR(mc->smmu)); in tegra_mc_probe()
689 mc->smmu = NULL; in tegra_mc_probe()
693 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { in tegra_mc_probe()
694 mc->gart = tegra_gart_probe(&pdev->dev, mc); in tegra_mc_probe()
695 if (IS_ERR(mc->gart)) { in tegra_mc_probe()
696 dev_err(&pdev->dev, "failed to probe GART: %ld\n", in tegra_mc_probe()
697 PTR_ERR(mc->gart)); in tegra_mc_probe()
698 mc->gart = NULL; in tegra_mc_probe()
710 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { in tegra_mc_suspend()
711 err = tegra_gart_suspend(mc->gart); in tegra_mc_suspend()
724 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { in tegra_mc_resume()
725 err = tegra_gart_resume(mc->gart); in tegra_mc_resume()
740 .name = "tegra-mc",
757 MODULE_LICENSE("GPL v2");