1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2012 - 2018 Xilinx, Inc
17 #include <linux/pl353-smc.h>
26 #define PL353_SMC_ECC_STATUS_OFFS	0x400	/* ECC status register */
27 #define PL353_SMC_ECC_MEMCFG_OFFS	0x404	/* ECC mem config reg */
28 #define PL353_SMC_ECC_MEMCMD1_OFFS	0x408	/* ECC mem cmd1 reg */
29 #define PL353_SMC_ECC_MEMCMD2_OFFS	0x40C	/* ECC mem cmd2 reg */
30 #define PL353_SMC_ECC_VALUE0_OFFS	0x418	/* ECC value 0 reg */
59 /* ECC status register specific constants */
63 /* ECC memory config register specific constants */
68 #define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */ \
82  * struct pl353_smc_data - Private smc driver structure
95  * pl353_smc_set_buswidth - Set memory buswidth
102 		return -EINVAL;  in pl353_smc_set_buswidth()
113  * pl353_smc_set_cycles - Set memory timing parameters
114  * @timings: NAND controller timing parameters
116  * Sets NAND chip specific timing parameters.
148  * pl353_smc_ecc_is_busy - Read ecc busy flag
159  * pl353_smc_get_ecc_val - Read ecc_valueN registers
179  * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
195  * pl353_smc_clr_nand_int - Clear NAND interrupt
205  * pl353_smc_set_ecc_mode - Set SMC ECC mode
206  * @mode: ECC mode (BYPASS, APB, MEM)
209 int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)  in pl353_smc_set_ecc_mode()  argument
214 	switch (mode) {  in pl353_smc_set_ecc_mode()
221 		reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;  in pl353_smc_set_ecc_mode()
226 		ret = -EINVAL;  in pl353_smc_set_ecc_mode()
234  * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
235  * @pg_sz: ECC page size
256 		return -EINVAL;  in pl353_smc_set_ecc_pg_size()
272 	clk_disable(pl353_smc->memclk);  in pl353_smc_suspend()
273 	clk_disable(pl353_smc->aclk);  in pl353_smc_suspend()
283 	ret = clk_enable(pl353_smc->aclk);  in pl353_smc_resume()
289 	ret = clk_enable(pl353_smc->memclk);  in pl353_smc_resume()
292 		clk_disable(pl353_smc->aclk);  in pl353_smc_resume()
305  * pl353_smc_init_nand_interface - Initialize the NAND interface
321 	/* Wait till the ECC operation is complete */  in pl353_smc_init_nand_interface()
340 		.compatible = "cfi-flash"
343 		.compatible = "arm,pl353-nand-r2p1",
355 	struct device_node *of_node = adev->dev.of_node;  in pl353_smc_probe()
360 	pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);  in pl353_smc_probe()
362 		return -ENOMEM;  in pl353_smc_probe()
364 	/* Get the NAND controller virtual address */  in pl353_smc_probe()
365 	res = &adev->res;  in pl353_smc_probe()
366 	pl353_smc_base = devm_ioremap_resource(&adev->dev, res);  in pl353_smc_probe()
370 	pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");  in pl353_smc_probe()
371 	if (IS_ERR(pl353_smc->aclk)) {  in pl353_smc_probe()
372 		dev_err(&adev->dev, "aclk clock not found.\n");  in pl353_smc_probe()
373 		return PTR_ERR(pl353_smc->aclk);  in pl353_smc_probe()
376 	pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk");  in pl353_smc_probe()
377 	if (IS_ERR(pl353_smc->memclk)) {  in pl353_smc_probe()
378 		dev_err(&adev->dev, "memclk clock not found.\n");  in pl353_smc_probe()
379 		return PTR_ERR(pl353_smc->memclk);  in pl353_smc_probe()
382 	err = clk_prepare_enable(pl353_smc->aclk);  in pl353_smc_probe()
384 		dev_err(&adev->dev, "Unable to enable AXI clock.\n");  in pl353_smc_probe()
388 	err = clk_prepare_enable(pl353_smc->memclk);  in pl353_smc_probe()
390 		dev_err(&adev->dev, "Unable to enable memory clock.\n");  in pl353_smc_probe()
404 			dev_warn(&adev->dev, "unsupported child node\n");  in pl353_smc_probe()
410 		dev_err(&adev->dev, "no matching children\n");  in pl353_smc_probe()
414 	init = match->data;  in pl353_smc_probe()
417 	of_platform_device_create(child, NULL, &adev->dev);  in pl353_smc_probe()
422 	clk_disable_unprepare(pl353_smc->memclk);  in pl353_smc_probe()
424 	clk_disable_unprepare(pl353_smc->aclk);  in pl353_smc_probe()
433 	clk_disable_unprepare(pl353_smc->memclk);  in pl353_smc_remove()
434 	clk_disable_unprepare(pl353_smc->aclk);  in pl353_smc_remove()
451 		.name = "pl353-smc",