1 // SPDX-License-Identifier: GPL-2.0-only
3  * JZ4780 NAND/external memory controller (NEMC)
6  * Author: Alex Smith <alex@alex-smith.me.uk>
21 #include <linux/jz4780-nemc.h>
23 #define NEMC_SMCRn(n)		(0x14 + (((n) - 1) * 4))
43 #define NEMC_NFCSR_NFEn(n)	BIT(((n) - 1) << 1)
44 #define NEMC_NFCSR_NFCEn(n)	BIT((((n) - 1) << 1) + 1)
45 #define NEMC_NFCSR_TNFEn(n)	BIT(16 + (n) - 1)
62  * jz4780_nemc_num_banks() - count the number of banks referenced by a device
76 	while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {  in jz4780_nemc_num_banks()
89  * jz4780_nemc_set_type() - set the type of device connected to a bank
97 	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);  in jz4780_nemc_set_type()
100 	nfcsr = readl(nemc->base + NEMC_NFCSR);  in jz4780_nemc_set_type()
102 	/* TODO: Support toggle NAND devices. */  in jz4780_nemc_set_type()
113 	writel(nfcsr, nemc->base + NEMC_NFCSR);  in jz4780_nemc_set_type()
118  * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
123  * (De-)asserts the chip enable pin for the NAND device connected to the
128 	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);  in jz4780_nemc_assert()
131 	nfcsr = readl(nemc->base + NEMC_NFCSR);  in jz4780_nemc_assert()
138 	writel(nfcsr, nemc->base + NEMC_NFCSR);  in jz4780_nemc_assert()
146 	rate = clk_get_rate(nemc->clk);  in jz4780_nemc_clk_period()
156 	return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;  in jz4780_nemc_ns_to_cycles()
172 		/* 11 - 12 -> 12 cycles */  in jz4780_nemc_configure_bank()
175 		/* 13 - 15 -> 15 cycles */  in jz4780_nemc_configure_bank()
178 		/* 16 - 20 -> 20 cycles */  in jz4780_nemc_configure_bank()
181 		/* 21 - 25 -> 25 cycles */  in jz4780_nemc_configure_bank()
184 		/* 26 - 31 -> 31 cycles */  in jz4780_nemc_configure_bank()
188 	smcr = readl(nemc->base + NEMC_SMCRn(bank));  in jz4780_nemc_configure_bank()
191 	if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {  in jz4780_nemc_configure_bank()
202 			dev_err(nemc->dev, "unsupported bus width: %u\n", val);  in jz4780_nemc_configure_bank()
207 	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {  in jz4780_nemc_configure_bank()
210 		if (cycles > nemc->soc_info->tas_tah_cycles_max) {  in jz4780_nemc_configure_bank()
211 			dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",  in jz4780_nemc_configure_bank()
219 	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {  in jz4780_nemc_configure_bank()
222 		if (cycles > nemc->soc_info->tas_tah_cycles_max) {  in jz4780_nemc_configure_bank()
223 			dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",  in jz4780_nemc_configure_bank()
231 	if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {  in jz4780_nemc_configure_bank()
235 			dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",  in jz4780_nemc_configure_bank()
243 	if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {  in jz4780_nemc_configure_bank()
247 			dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",  in jz4780_nemc_configure_bank()
255 	if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {  in jz4780_nemc_configure_bank()
259 			dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",  in jz4780_nemc_configure_bank()
267 	writel(smcr, nemc->base + NEMC_SMCRn(bank));  in jz4780_nemc_configure_bank()
273 	struct device *dev = &pdev->dev;  in jz4780_nemc_probe()
284 		return -ENOMEM;  in jz4780_nemc_probe()
286 	nemc->soc_info = device_get_match_data(dev);  in jz4780_nemc_probe()
287 	if (!nemc->soc_info)  in jz4780_nemc_probe()
288 		return -EINVAL;  in jz4780_nemc_probe()
290 	spin_lock_init(&nemc->lock);  in jz4780_nemc_probe()
291 	nemc->dev = dev;  in jz4780_nemc_probe()
301 	if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {  in jz4780_nemc_probe()
303 		return -EBUSY;  in jz4780_nemc_probe()
306 	nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);  in jz4780_nemc_probe()
307 	if (IS_ERR(nemc->base)) {  in jz4780_nemc_probe()
309 		return PTR_ERR(nemc->base);  in jz4780_nemc_probe()
312 	writel(0, nemc->base + NEMC_NFCSR);  in jz4780_nemc_probe()
314 	nemc->clk = devm_clk_get(dev, NULL);  in jz4780_nemc_probe()
315 	if (IS_ERR(nemc->clk)) {  in jz4780_nemc_probe()
317 		return PTR_ERR(nemc->clk);  in jz4780_nemc_probe()
320 	ret = clk_prepare_enable(nemc->clk);  in jz4780_nemc_probe()
326 	nemc->clk_period = jz4780_nemc_clk_period(nemc);  in jz4780_nemc_probe()
327 	if (!nemc->clk_period) {  in jz4780_nemc_probe()
329 		clk_disable_unprepare(nemc->clk);  in jz4780_nemc_probe()
330 		return -EINVAL;  in jz4780_nemc_probe()
339 	for_each_child_of_node(nemc->dev->of_node, child) {  in jz4780_nemc_probe()
345 				dev_err(nemc->dev,  in jz4780_nemc_probe()
358 			dev_err(nemc->dev, "%pOF has no addresses\n",  in jz4780_nemc_probe()
361 		} else if (nemc->banks_present & referenced) {  in jz4780_nemc_probe()
362 			dev_err(nemc->dev, "%pOF conflicts with another node\n",  in jz4780_nemc_probe()
376 			if (of_platform_device_create(child, NULL, nemc->dev))  in jz4780_nemc_probe()
377 				nemc->banks_present |= referenced;  in jz4780_nemc_probe()
382 	dev_info(dev, "JZ4780 NEMC initialised\n");  in jz4780_nemc_probe()
390 	clk_disable_unprepare(nemc->clk);  in jz4780_nemc_remove()
403 	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
404 	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
412 		.name	= "jz4780-nemc",