Lines Matching refs:reg_w_val
168 static void reg_w_val(struct gspca_dev *gspca_dev, in reg_w_val() function
214 reg_w_val(gspca_dev, ET_I2C_BASE, 0x40); in i2c_w()
218 reg_w_val(gspca_dev, ET_I2C_COUNT, ptchcount); in i2c_w()
220 reg_w_val(gspca_dev, ET_I2C_REG, reg); in i2c_w()
222 reg_w_val(gspca_dev, ET_I2C_DATA0 + len, buffer[len]); in i2c_w()
230 reg_w_val(gspca_dev, ET_I2C_BASE, 0x40); in i2c_r()
233 reg_w_val(gspca_dev, ET_I2C_COUNT, 0x11); in i2c_r()
234 reg_w_val(gspca_dev, ET_I2C_REG, reg); /* set the register base */ in i2c_r()
235 reg_w_val(gspca_dev, ET_I2C_PREFETCH, 0x02); /* prefetch */ in i2c_r()
236 reg_w_val(gspca_dev, ET_I2C_PREFETCH, 0x00); in i2c_r()
258 reg_w_val(gspca_dev, ET_GPIO_OUT, in et_video()
273 reg_w_val(gspca_dev, ET_GPIO_DIR_CTRL, 0x2f); in Et_init2()
274 reg_w_val(gspca_dev, ET_GPIO_OUT, 0x10); in Et_init2()
276 reg_w_val(gspca_dev, ET_ClCK, 0x14); /* 0x14 // 0x16 enabled pattern */ in Et_init2()
277 reg_w_val(gspca_dev, ET_CTRL, 0x1b); in Et_init2()
284 reg_w_val(gspca_dev, ET_COMP, value); in Et_init2()
285 reg_w_val(gspca_dev, ET_MAXQt, 0x1f); in Et_init2()
286 reg_w_val(gspca_dev, ET_MINQt, 0x04); in Et_init2()
288 reg_w_val(gspca_dev, ET_REG1d, 0xff); in Et_init2()
289 reg_w_val(gspca_dev, ET_REG1e, 0xff); in Et_init2()
290 reg_w_val(gspca_dev, ET_REG1f, 0xff); in Et_init2()
291 reg_w_val(gspca_dev, ET_REG20, 0x35); in Et_init2()
292 reg_w_val(gspca_dev, ET_REG21, 0x01); in Et_init2()
293 reg_w_val(gspca_dev, ET_REG22, 0x00); in Et_init2()
294 reg_w_val(gspca_dev, ET_REG23, 0xff); in Et_init2()
295 reg_w_val(gspca_dev, ET_REG24, 0xff); in Et_init2()
296 reg_w_val(gspca_dev, ET_REG25, 0x0f); in Et_init2()
298 reg_w_val(gspca_dev, 0x30, 0x11); /* 0x30 */ in Et_init2()
299 reg_w_val(gspca_dev, 0x31, 0x40); in Et_init2()
300 reg_w_val(gspca_dev, 0x32, 0x00); in Et_init2()
301 reg_w_val(gspca_dev, ET_O_RED, 0x00); /* 0x34 */ in Et_init2()
302 reg_w_val(gspca_dev, ET_O_GREEN1, 0x00); in Et_init2()
303 reg_w_val(gspca_dev, ET_O_BLUE, 0x00); in Et_init2()
304 reg_w_val(gspca_dev, ET_O_GREEN2, 0x00); in Et_init2()
306 reg_w_val(gspca_dev, ET_G_RED, 0x80); /* 0x4d */ in Et_init2()
307 reg_w_val(gspca_dev, ET_G_GREEN1, 0x80); in Et_init2()
308 reg_w_val(gspca_dev, ET_G_BLUE, 0x80); in Et_init2()
309 reg_w_val(gspca_dev, ET_G_GREEN2, 0x80); in Et_init2()
310 reg_w_val(gspca_dev, ET_G_GR_H, 0x00); in Et_init2()
311 reg_w_val(gspca_dev, ET_G_GB_H, 0x00); /* 0x52 */ in Et_init2()
313 reg_w_val(gspca_dev, 0x61, 0x80); /* use cmc_out */ in Et_init2()
314 reg_w_val(gspca_dev, 0x62, 0x02); in Et_init2()
315 reg_w_val(gspca_dev, 0x63, 0x03); in Et_init2()
316 reg_w_val(gspca_dev, 0x64, 0x14); in Et_init2()
317 reg_w_val(gspca_dev, 0x65, 0x0e); in Et_init2()
318 reg_w_val(gspca_dev, 0x66, 0x02); in Et_init2()
319 reg_w_val(gspca_dev, 0x67, 0x02); in Et_init2()
322 reg_w_val(gspca_dev, ET_SYNCHRO, 0x8f); /* 0x68 */ in Et_init2()
323 reg_w_val(gspca_dev, ET_STARTX, 0x69); /* 0x6a //0x69 */ in Et_init2()
324 reg_w_val(gspca_dev, ET_STARTY, 0x0d); /* 0x0d //0x0c */ in Et_init2()
325 reg_w_val(gspca_dev, ET_WIDTH_LOW, 0x80); in Et_init2()
326 reg_w_val(gspca_dev, ET_HEIGTH_LOW, 0xe0); in Et_init2()
327 reg_w_val(gspca_dev, ET_W_H_HEIGTH, 0x60); /* 6d */ in Et_init2()
328 reg_w_val(gspca_dev, ET_REG6e, 0x86); in Et_init2()
329 reg_w_val(gspca_dev, ET_REG6f, 0x01); in Et_init2()
330 reg_w_val(gspca_dev, ET_REG70, 0x26); in Et_init2()
331 reg_w_val(gspca_dev, ET_REG71, 0x7a); in Et_init2()
332 reg_w_val(gspca_dev, ET_REG72, 0x01); in Et_init2()
334 reg_w_val(gspca_dev, ET_REG73, 0x00); in Et_init2()
335 reg_w_val(gspca_dev, ET_REG74, 0x18); /* 0x28 */ in Et_init2()
336 reg_w_val(gspca_dev, ET_REG75, 0x0f); /* 0x01 */ in Et_init2()
338 reg_w_val(gspca_dev, 0x8a, 0x20); in Et_init2()
339 reg_w_val(gspca_dev, 0x8d, 0x0f); in Et_init2()
340 reg_w_val(gspca_dev, 0x8e, 0x08); in Et_init2()
342 reg_w_val(gspca_dev, 0x03, 0x08); in Et_init2()
343 reg_w_val(gspca_dev, ET_PXL_CLK, 0x03); in Et_init2()
344 reg_w_val(gspca_dev, 0x81, 0xff); in Et_init2()
345 reg_w_val(gspca_dev, 0x80, 0x00); in Et_init2()
346 reg_w_val(gspca_dev, 0x81, 0xff); in Et_init2()
347 reg_w_val(gspca_dev, 0x80, 0x20); in Et_init2()
348 reg_w_val(gspca_dev, 0x03, 0x01); in Et_init2()
349 reg_w_val(gspca_dev, 0x03, 0x00); in Et_init2()
350 reg_w_val(gspca_dev, 0x03, 0x08); in Et_init2()
365 reg_w_val(gspca_dev, ET_PXL_CLK, value); in Et_init2()
370 reg_w_val(gspca_dev, 0x81, 0x47); /* 0x47; */ in Et_init2()
371 reg_w_val(gspca_dev, 0x80, 0x40); /* 0x40; */ in Et_init2()
376 reg_w_val(gspca_dev, 0x81, 0x30); /* 0x20; - set brightness */ in Et_init2()
377 reg_w_val(gspca_dev, 0x80, 0x20); /* 0x20; */ in Et_init2()
385 reg_w_val(gspca_dev, ET_O_RED + i, val); in setbrightness()
445 reg_w_val(gspca_dev, ET_GPIO_DIR_CTRL, 7); in Et_init1()
447 reg_w_val(gspca_dev, ET_RESET_ALL, 1); in Et_init1()
448 reg_w_val(gspca_dev, ET_RESET_ALL, 0); in Et_init1()
449 reg_w_val(gspca_dev, ET_ClCK, 0x10); in Et_init1()
450 reg_w_val(gspca_dev, ET_CTRL, 0x19); in Et_init1()
459 reg_w_val(gspca_dev, ET_COMP, value); in Et_init1()
460 reg_w_val(gspca_dev, ET_MAXQt, 0x1d); in Et_init1()
461 reg_w_val(gspca_dev, ET_MINQt, 0x02); in Et_init1()
463 reg_w_val(gspca_dev, ET_REG1d, 0xff); in Et_init1()
464 reg_w_val(gspca_dev, ET_REG1e, 0xff); in Et_init1()
465 reg_w_val(gspca_dev, ET_REG1f, 0xff); in Et_init1()
466 reg_w_val(gspca_dev, ET_REG20, 0x35); in Et_init1()
467 reg_w_val(gspca_dev, ET_REG21, 0x01); in Et_init1()
468 reg_w_val(gspca_dev, ET_REG22, 0x00); in Et_init1()
469 reg_w_val(gspca_dev, ET_REG23, 0xf7); in Et_init1()
470 reg_w_val(gspca_dev, ET_REG24, 0xff); in Et_init1()
471 reg_w_val(gspca_dev, ET_REG25, 0x07); in Et_init1()
473 reg_w_val(gspca_dev, ET_G_RED, 0x80); in Et_init1()
474 reg_w_val(gspca_dev, ET_G_GREEN1, 0x80); in Et_init1()
475 reg_w_val(gspca_dev, ET_G_BLUE, 0x80); in Et_init1()
476 reg_w_val(gspca_dev, ET_G_GREEN2, 0x80); in Et_init1()
477 reg_w_val(gspca_dev, ET_G_GR_H, 0x00); in Et_init1()
478 reg_w_val(gspca_dev, ET_G_GB_H, 0x00); in Et_init1()
480 reg_w_val(gspca_dev, ET_SYNCHRO, 0xf0); in Et_init1()
481 reg_w_val(gspca_dev, ET_STARTX, 0x56); /* 0x56 */ in Et_init1()
482 reg_w_val(gspca_dev, ET_STARTY, 0x05); /* 0x04 */ in Et_init1()
483 reg_w_val(gspca_dev, ET_WIDTH_LOW, 0x60); in Et_init1()
484 reg_w_val(gspca_dev, ET_HEIGTH_LOW, 0x20); in Et_init1()
485 reg_w_val(gspca_dev, ET_W_H_HEIGTH, 0x50); in Et_init1()
486 reg_w_val(gspca_dev, ET_REG6e, 0x86); in Et_init1()
487 reg_w_val(gspca_dev, ET_REG6f, 0x01); in Et_init1()
488 reg_w_val(gspca_dev, ET_REG70, 0x86); in Et_init1()
489 reg_w_val(gspca_dev, ET_REG71, 0x14); in Et_init1()
490 reg_w_val(gspca_dev, ET_REG72, 0x00); in Et_init1()
492 reg_w_val(gspca_dev, ET_REG73, 0x00); in Et_init1()
493 reg_w_val(gspca_dev, ET_REG74, 0x00); in Et_init1()
494 reg_w_val(gspca_dev, ET_REG75, 0x0a); in Et_init1()
495 reg_w_val(gspca_dev, ET_I2C_CLK, 0x04); in Et_init1()
496 reg_w_val(gspca_dev, ET_PXL_CLK, 0x01); in Et_init1()
564 reg_w_val(gspca_dev, ET_RESET_ALL, 0x08); in sd_init()
581 reg_w_val(gspca_dev, ET_RESET_ALL, 0x08); in sd_start()