204 	u8 r12, r15, r17, r18, r3D, r82, r84, r89;  in mxl111sf_config_pin_mux_modes()  local
230 	ret = mxl111sf_read_reg(state, 0x3D, &r3D);  in mxl111sf_config_pin_mux_modes()
243 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
249 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
271 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
277 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
299 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
305 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
327 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
333 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
355 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
361 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
383 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
389 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
411 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
417 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
439 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
445 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
467 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
473 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
496 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
502 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
539 	ret = mxl111sf_write_reg(state, 0x3D, r3D);  in mxl111sf_config_pin_mux_modes()