Lines Matching full:receiver

201 #define IT87_RCR	0x02	/* receiver control register */
205 #define IT87_RSR	0x06	/* receiver status register */
214 #define IT87_RDAIE	0x02	/* receiver data available interrupt enable */
215 #define IT87_RFOIE	0x04	/* receiver FIFO overrun interrupt enable */
221 #define IT87_RXDCR	0x07	/* receiver demodulation carrier range mask */
222 #define IT87_RXACT	0x08	/* receiver active */
223 #define IT87_RXEND	0x10	/* receiver demodulation enable */
224 #define IT87_RXEN	0x20	/* receiver enable */
226 #define IT87_RDWOS	0x80	/* receiver data without sync */
250 #define IT87_RXFBC	0x3f	/* receiver FIFO byte count mask */
251 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
258 #define IT87_II_RXDS	0x04	/* receiver data stored */
259 #define IT87_II_RXFO	0x06	/* receiver FIFO overrun */
285 #define IT85_C0RCR	0x05	/* receiver control register */
291 #define IT85_C0RFSR	0x0b	/* receiver FIFO status register */
316 #define IT85_RDAI	0x02	/* receiver data available interrupt */
317 #define IT85_RFOI	0x04	/* receiver FIFO overrun interrupt */
325 #define IT85_RXDCR	0x07	/* receiver demodulation carrier range mask */
326 #define IT85_RXACT	0x08	/* receiver active */
327 #define IT85_RXEND	0x10	/* receiver demodulation enable */
328 #define IT85_RDWOS	0x20	/* receiver data without sync */
329 #define IT85_RXEN	0x80	/* receiver enable */
351 #define IT85_RXFBC	0x3f	/* receiver FIFO count mask */
352 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
391 #define IT8708_C0RFSR	0x04	/* receiver FIFO status register */
392 #define IT8708_C0RCR	0x05	/* receiver control register */
457 #define IT8709_RFSR	0x1f	/* receiver FIFO status register */