Lines Matching +full:0 +full:x4e
18 #define VENDOR_ID_FINTEK 0x1934
88 CMD_HEADER = 0,
101 #define BUF_PULSE_BIT 0x80
102 #define BUF_LEN_MASK 0x1f
103 #define BUF_SAMPLE_MASK 0x7f
105 #define BUF_COMMAND_HEADER 0x9f
106 #define BUF_COMMAND_MASK 0xe0
107 #define BUF_COMMAND_NULL 0x00
108 #define BUF_HW_CMD_HEADER 0xff
109 #define BUF_CMD_G_REVISION 0x0b
110 #define BUF_CMD_S_CARRIER 0x06
111 #define BUF_CMD_S_TIMEOUT 0x0c
112 #define BUF_CMD_SIG_END 0x01
113 #define BUF_CMD_S_TXMASK 0x08
114 #define BUF_CMD_S_RXSENSOR 0x14
115 #define BUF_RSP_PULSE_COUNT 0x15
124 #define CR_INDEX_PORT 0x2e
125 #define CR_DATA_PORT 0x2f
128 #define CR_INDEX_PORT2 0x4e
129 #define CR_DATA_PORT2 0x4f
133 * active. 1 = 0x4e, 0 = 0x2e
135 #define PORT_SEL_PORT_4E_EN 0x10
138 #define CONFIG_REG_ENABLE 0x87
139 #define CONFIG_REG_DISABLE 0xaa
142 #define CHIP_ID_HIGH_F71809U 0x04
143 #define CHIP_ID_LOW_F71809U 0x08
149 #define GCR_SOFTWARE_RESET 0x02 /* 0x00 */
150 #define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */
151 #define GCR_CHIP_ID_HI 0x20 /* 0x04 */
152 #define GCR_CHIP_ID_LO 0x21 /* 0x08 */
153 #define GCR_VENDOR_ID_HI 0x23 /* 0x19 */
154 #define GCR_VENDOR_ID_LO 0x24 /* 0x34 */
155 #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */
156 #define GCR_KBMOUSE_WAKEUP 0x27
158 #define LOGICAL_DEV_DISABLE 0x00
159 #define LOGICAL_DEV_ENABLE 0x01
162 #define LOGICAL_DEV_CIR_REV1 0x05
163 #define LOGICAL_DEV_CIR_REV2 0x08
165 /* CIR Logical Device (LDN 0x08) config registers */
166 #define CIR_CR_COMMAND_INDEX 0x04
167 #define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host
169 command to IR, host must clear to 0. */
170 #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write command data */
171 #define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
172 0x33 = rx + 1 tx */
173 #define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */
174 #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */
175 #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */
176 #define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */
177 #define CIR_CR_PSOUT_STATUS 0xf1
178 #define CIR_CR_WAKE_KEY3_ADDR 0xf8
179 #define CIR_CR_WAKE_KEY3_CODE 0xf9
180 #define CIR_CR_WAKE_KEY3_DC 0xfa
181 #define CIR_CR_WAKE_CONTROL 0xfb
182 #define CIR_CR_WAKE_KEY12_ADDR 0xfc
183 #define CIR_CR_WAKE_KEY4_ADDR 0xfd
184 #define CIR_CR_WAKE_KEY5_ADDR 0xfe
186 #define CLASS_RX_ONLY 0xff
187 #define CLASS_RX_2TX 0x66
188 #define CLASS_RX_1TX 0x33
191 #define CIR_STATUS 0x00
192 #define CIR_RX_DATA 0x01
193 #define CIR_TX_CONTROL 0x02
194 #define CIR_TX_DATA 0x03
195 #define CIR_CONTROL 0x04
198 #define LOGICAL_DEV_ACPI 0x01
199 #define LDEV_ACPI_WAKE_EN_REG 0xe8
200 #define ACPI_WAKE_EN_CIR_BIT 0x04
202 #define LDEV_ACPI_PME_EN_REG 0xf0
203 #define LDEV_ACPI_PME_CLR_REG 0xf1
204 #define ACPI_PME_CIR_BIT 0x02
206 #define LDEV_ACPI_STATE_REG 0xf4
207 #define ACPI_STATE_CIR_BIT 0x20
210 * CIR status register (0x00):
211 * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
215 * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
217 #define CIR_STATUS_IRQ_EN 0x80
218 #define CIR_STATUS_TX_FINISH 0x08
219 #define CIR_STATUS_TX_UNDERRUN 0x04
220 #define CIR_STATUS_RX_TIMEOUT 0x02
221 #define CIR_STATUS_RX_RECEIVE 0x01
222 #define CIR_STATUS_IRQ_MASK 0x0f
225 * CIR TX control register (0x02):
229 #define CIR_TX_CONTROL_TX_START 0x80
230 #define CIR_TX_CONTROL_TX_END 0x40