Lines Matching full:vin
3 * Driver for Renesas R-Car VIN
19 #include "rcar-vin.h"
25 /* Register offsets for R-Car VIN */
78 /* Register bit fields for R-Car VIN */
147 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset) in rvin_write() argument
149 iowrite32(value, vin->base + offset); in rvin_write()
152 static u32 rvin_read(struct rvin_dev *vin, u32 offset) in rvin_read() argument
154 return ioread32(vin->base + offset); in rvin_read()
479 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs) in rvin_set_coeff() argument
500 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
501 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG); in rvin_set_coeff()
502 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG); in rvin_set_coeff()
504 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG); in rvin_set_coeff()
505 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG); in rvin_set_coeff()
506 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG); in rvin_set_coeff()
508 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG); in rvin_set_coeff()
509 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG); in rvin_set_coeff()
510 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG); in rvin_set_coeff()
512 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG); in rvin_set_coeff()
513 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG); in rvin_set_coeff()
514 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG); in rvin_set_coeff()
516 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG); in rvin_set_coeff()
517 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG); in rvin_set_coeff()
518 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG); in rvin_set_coeff()
520 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG); in rvin_set_coeff()
521 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG); in rvin_set_coeff()
522 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG); in rvin_set_coeff()
524 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG); in rvin_set_coeff()
525 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG); in rvin_set_coeff()
526 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG); in rvin_set_coeff()
528 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG); in rvin_set_coeff()
529 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG); in rvin_set_coeff()
530 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG); in rvin_set_coeff()
533 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin) in rvin_crop_scale_comp_gen2() argument
539 crop_height = vin->crop.height; in rvin_crop_scale_comp_gen2()
540 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
544 if (crop_height != vin->compose.height) in rvin_crop_scale_comp_gen2()
545 ys = (4096 * crop_height) / vin->compose.height; in rvin_crop_scale_comp_gen2()
546 rvin_write(vin, ys, VNYS_REG); in rvin_crop_scale_comp_gen2()
549 if (vin->crop.width != vin->compose.width) in rvin_crop_scale_comp_gen2()
550 xs = (4096 * vin->crop.width) / vin->compose.width; in rvin_crop_scale_comp_gen2()
556 rvin_write(vin, xs, VNXS_REG); in rvin_crop_scale_comp_gen2()
562 rvin_set_coeff(vin, xs); in rvin_crop_scale_comp_gen2()
565 rvin_write(vin, 0, VNSPPOC_REG); in rvin_crop_scale_comp_gen2()
566 rvin_write(vin, 0, VNSLPOC_REG); in rvin_crop_scale_comp_gen2()
567 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG); in rvin_crop_scale_comp_gen2()
569 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
570 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
572 rvin_write(vin, vin->format.height - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
574 vin_dbg(vin, in rvin_crop_scale_comp_gen2()
576 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_crop_scale_comp_gen2()
577 vin->crop.top, ys, xs, vin->format.width, vin->format.height, in rvin_crop_scale_comp_gen2()
581 void rvin_crop_scale_comp(struct rvin_dev *vin) in rvin_crop_scale_comp() argument
587 rvin_write(vin, vin->crop.left, VNSPPRC_REG); in rvin_crop_scale_comp()
588 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG); in rvin_crop_scale_comp()
589 rvin_write(vin, vin->crop.top, VNSLPRC_REG); in rvin_crop_scale_comp()
590 rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG); in rvin_crop_scale_comp()
593 if (vin->info->model != RCAR_GEN3) in rvin_crop_scale_comp()
594 rvin_crop_scale_comp_gen2(vin); in rvin_crop_scale_comp()
596 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_crop_scale_comp()
597 stride = vin->format.bytesperline / fmt->bpp; in rvin_crop_scale_comp()
602 switch (vin->format.pixelformat) { in rvin_crop_scale_comp()
613 rvin_write(vin, stride, VNIS_REG); in rvin_crop_scale_comp()
620 static int rvin_setup(struct rvin_dev *vin) in rvin_setup() argument
625 switch (vin->format.field) { in rvin_setup()
636 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60) in rvin_setup()
662 switch (vin->mbus_code) { in rvin_setup()
674 if (!vin->is_csi && in rvin_setup()
675 vin->parallel->mbus_type == V4L2_MBUS_BT656) in rvin_setup()
687 if (!vin->is_csi && in rvin_setup()
688 vin->parallel->mbus_type == V4L2_MBUS_BT656) in rvin_setup()
706 if (vin->info->model == RCAR_GEN3) in rvin_setup()
711 if (!vin->is_csi) { in rvin_setup()
713 if (!(vin->parallel->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) in rvin_setup()
717 if (!(vin->parallel->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) in rvin_setup()
721 if (vin->parallel->bus.flags & V4L2_MBUS_DATA_ENABLE_LOW) in rvin_setup()
724 switch (vin->mbus_code) { in rvin_setup()
726 if (vin->parallel->bus.bus_width == 8 && in rvin_setup()
727 vin->parallel->bus.data_shift == 8) in rvin_setup()
738 switch (vin->format.pixelformat) { in rvin_setup()
741 rvin_write(vin, in rvin_setup()
742 ALIGN(vin->format.bytesperline * vin->format.height, in rvin_setup()
744 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ? in rvin_setup()
767 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
770 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB; in rvin_setup()
779 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
780 vin->format.pixelformat); in rvin_setup()
791 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
793 if (vin->is_csi) in rvin_setup()
803 rvin_write(vin, interrupts, VNINTS_REG); in rvin_setup()
805 rvin_write(vin, interrupts, VNIE_REG); in rvin_setup()
807 rvin_write(vin, dmr, VNDMR_REG); in rvin_setup()
808 rvin_write(vin, dmr2, VNDMR2_REG); in rvin_setup()
811 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG); in rvin_setup()
816 static void rvin_disable_interrupts(struct rvin_dev *vin) in rvin_disable_interrupts() argument
818 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
821 static u32 rvin_get_interrupt_status(struct rvin_dev *vin) in rvin_get_interrupt_status() argument
823 return rvin_read(vin, VNINTS_REG); in rvin_get_interrupt_status()
826 static void rvin_ack_interrupt(struct rvin_dev *vin) in rvin_ack_interrupt() argument
828 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG); in rvin_ack_interrupt()
831 static bool rvin_capture_active(struct rvin_dev *vin) in rvin_capture_active() argument
833 return rvin_read(vin, VNMS_REG) & VNMS_CA; in rvin_capture_active()
836 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms) in rvin_get_active_field() argument
838 if (vin->format.field == V4L2_FIELD_ALTERNATE) { in rvin_get_active_field()
845 return vin->format.field; in rvin_get_active_field()
848 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr) in rvin_set_slot_addr() argument
854 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_set_slot_addr()
860 offsetx = vin->compose.left * fmt->bpp; in rvin_set_slot_addr()
861 offsety = vin->compose.top * vin->format.bytesperline; in rvin_set_slot_addr()
871 rvin_write(vin, offset, VNMB_REG(slot)); in rvin_set_slot_addr()
880 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot) in rvin_fill_hw_slot() argument
888 if (WARN_ON(vin->buf_hw[slot].buffer)) in rvin_fill_hw_slot()
893 if (vin->buf_hw[prev].type == HALF_TOP) { in rvin_fill_hw_slot()
894 vbuf = vin->buf_hw[prev].buffer; in rvin_fill_hw_slot()
895 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
896 vin->buf_hw[slot].type = HALF_BOTTOM; in rvin_fill_hw_slot()
897 switch (vin->format.pixelformat) { in rvin_fill_hw_slot()
900 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
901 vin->format.sizeimage / 4; in rvin_fill_hw_slot()
904 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
905 vin->format.sizeimage / 2; in rvin_fill_hw_slot()
908 } else if (list_empty(&vin->buf_list)) { in rvin_fill_hw_slot()
909 vin->buf_hw[slot].buffer = NULL; in rvin_fill_hw_slot()
910 vin->buf_hw[slot].type = FULL; in rvin_fill_hw_slot()
911 phys_addr = vin->scratch_phys; in rvin_fill_hw_slot()
914 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list); in rvin_fill_hw_slot()
917 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
919 vin->buf_hw[slot].type = in rvin_fill_hw_slot()
920 V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ? in rvin_fill_hw_slot()
927 vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n", in rvin_fill_hw_slot()
928 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer); in rvin_fill_hw_slot()
930 vin->buf_hw[slot].phys = phys_addr; in rvin_fill_hw_slot()
931 rvin_set_slot_addr(vin, slot, phys_addr); in rvin_fill_hw_slot()
934 static int rvin_capture_start(struct rvin_dev *vin) in rvin_capture_start() argument
939 vin->buf_hw[slot].buffer = NULL; in rvin_capture_start()
940 vin->buf_hw[slot].type = FULL; in rvin_capture_start()
944 rvin_fill_hw_slot(vin, slot); in rvin_capture_start()
946 rvin_crop_scale_comp(vin); in rvin_capture_start()
948 ret = rvin_setup(vin); in rvin_capture_start()
952 vin_dbg(vin, "Starting to capture\n"); in rvin_capture_start()
955 rvin_write(vin, VNFC_C_FRAME, VNFC_REG); in rvin_capture_start()
957 vin->state = STARTING; in rvin_capture_start()
962 static void rvin_capture_stop(struct rvin_dev *vin) in rvin_capture_stop() argument
965 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
968 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG); in rvin_capture_stop()
980 struct rvin_dev *vin = data; in rvin_irq() local
986 spin_lock_irqsave(&vin->qlock, flags); in rvin_irq()
988 int_status = rvin_get_interrupt_status(vin); in rvin_irq()
992 rvin_ack_interrupt(vin); in rvin_irq()
996 if (vin->state == STOPPED) { in rvin_irq()
997 vin_dbg(vin, "IRQ while state stopped\n"); in rvin_irq()
1002 if (vin->state == STOPPING) { in rvin_irq()
1003 vin_dbg(vin, "IRQ while state stopping\n"); in rvin_irq()
1008 vnms = rvin_read(vin, VNMS_REG); in rvin_irq()
1015 if (vin->state == STARTING) { in rvin_irq()
1017 vin_dbg(vin, "Starting sync slot: %d\n", slot); in rvin_irq()
1021 vin_dbg(vin, "Capture start synced!\n"); in rvin_irq()
1022 vin->state = RUNNING; in rvin_irq()
1026 if (vin->buf_hw[slot].buffer) { in rvin_irq()
1031 if (vin->buf_hw[slot].type == HALF_TOP) { in rvin_irq()
1032 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1033 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1037 vin->buf_hw[slot].buffer->field = in rvin_irq()
1038 rvin_get_active_field(vin, vnms); in rvin_irq()
1039 vin->buf_hw[slot].buffer->sequence = vin->sequence; in rvin_irq()
1040 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns(); in rvin_irq()
1041 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf, in rvin_irq()
1043 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1046 vin_dbg(vin, "Dropping frame %u\n", vin->sequence); in rvin_irq()
1049 vin->sequence++; in rvin_irq()
1052 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1054 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_irq()
1060 static void return_all_buffers(struct rvin_dev *vin, in return_all_buffers() argument
1068 freed[i] = vin->buf_hw[i].buffer; in return_all_buffers()
1069 vin->buf_hw[i].buffer = NULL; in return_all_buffers()
1082 list_for_each_entry_safe(buf, node, &vin->buf_list, list) { in return_all_buffers()
1093 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_queue_setup() local
1097 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1100 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1107 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_prepare() local
1108 unsigned long size = vin->format.sizeimage; in rvin_buffer_prepare()
1111 vin_err(vin, "buffer too small (%lu < %lu)\n", in rvin_buffer_prepare()
1124 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_queue() local
1127 spin_lock_irqsave(&vin->qlock, flags); in rvin_buffer_queue()
1129 list_add_tail(to_buf_list(vbuf), &vin->buf_list); in rvin_buffer_queue()
1131 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_buffer_queue()
1134 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd, in rvin_mc_validate_format() argument
1153 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8) in rvin_mc_validate_format()
1157 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8) in rvin_mc_validate_format()
1161 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8) in rvin_mc_validate_format()
1165 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8) in rvin_mc_validate_format()
1171 vin->mbus_code = fmt.format.code; in rvin_mc_validate_format()
1185 switch (vin->format.field) { in rvin_mc_validate_format()
1196 /* Use VIN hardware to combine the two fields */ in rvin_mc_validate_format()
1207 if (fmt.format.width != vin->format.width || in rvin_mc_validate_format()
1208 fmt.format.height != vin->format.height || in rvin_mc_validate_format()
1209 fmt.format.code != vin->mbus_code) in rvin_mc_validate_format()
1215 static int rvin_set_stream(struct rvin_dev *vin, int on) in rvin_set_stream() argument
1224 if (!vin->info->use_mc) { in rvin_set_stream()
1225 ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream, in rvin_set_stream()
1231 pad = media_entity_remote_pad(&vin->pad); in rvin_set_stream()
1238 media_pipeline_stop(&vin->vdev.entity); in rvin_set_stream()
1242 ret = rvin_mc_validate_format(vin, sd, pad); in rvin_set_stream()
1248 * starts of multiple VIN instances as they might share in rvin_set_stream()
1252 mdev = vin->vdev.entity.graph_obj.mdev; in rvin_set_stream()
1254 pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe; in rvin_set_stream()
1255 ret = __media_pipeline_start(&vin->vdev.entity, pipe); in rvin_set_stream()
1264 media_pipeline_stop(&vin->vdev.entity); in rvin_set_stream()
1271 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_start_streaming() local
1276 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage, in rvin_start_streaming()
1277 &vin->scratch_phys, GFP_KERNEL); in rvin_start_streaming()
1278 if (!vin->scratch) { in rvin_start_streaming()
1279 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1280 return_all_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming()
1281 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1282 vin_err(vin, "Failed to allocate scratch buffer\n"); in rvin_start_streaming()
1286 ret = rvin_set_stream(vin, 1); in rvin_start_streaming()
1288 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1289 return_all_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming()
1290 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1294 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1296 vin->sequence = 0; in rvin_start_streaming()
1298 ret = rvin_capture_start(vin); in rvin_start_streaming()
1300 return_all_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming()
1301 rvin_set_stream(vin, 0); in rvin_start_streaming()
1304 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1307 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_start_streaming()
1308 vin->scratch_phys); in rvin_start_streaming()
1315 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_stop_streaming() local
1319 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1321 vin->state = STOPPING; in rvin_stop_streaming()
1326 rvin_capture_stop(vin); in rvin_stop_streaming()
1329 if (!rvin_capture_active(vin)) { in rvin_stop_streaming()
1330 vin->state = STOPPED; in rvin_stop_streaming()
1334 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1336 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1339 if (vin->state != STOPPED) { in rvin_stop_streaming()
1345 vin_err(vin, "Failed stop HW, something is seriously broken\n"); in rvin_stop_streaming()
1346 vin->state = STOPPED; in rvin_stop_streaming()
1350 return_all_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming()
1352 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1354 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1357 rvin_disable_interrupts(vin); in rvin_stop_streaming()
1360 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_stop_streaming()
1361 vin->scratch_phys); in rvin_stop_streaming()
1374 void rvin_dma_unregister(struct rvin_dev *vin) in rvin_dma_unregister() argument
1376 mutex_destroy(&vin->lock); in rvin_dma_unregister()
1378 v4l2_device_unregister(&vin->v4l2_dev); in rvin_dma_unregister()
1381 int rvin_dma_register(struct rvin_dev *vin, int irq) in rvin_dma_register() argument
1383 struct vb2_queue *q = &vin->queue; in rvin_dma_register()
1387 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev); in rvin_dma_register()
1391 mutex_init(&vin->lock); in rvin_dma_register()
1392 INIT_LIST_HEAD(&vin->buf_list); in rvin_dma_register()
1394 spin_lock_init(&vin->qlock); in rvin_dma_register()
1396 vin->state = STOPPED; in rvin_dma_register()
1399 vin->buf_hw[i].buffer = NULL; in rvin_dma_register()
1404 q->lock = &vin->lock; in rvin_dma_register()
1405 q->drv_priv = vin; in rvin_dma_register()
1411 q->dev = vin->dev; in rvin_dma_register()
1415 vin_err(vin, "failed to initialize VB2 queue\n"); in rvin_dma_register()
1420 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED, in rvin_dma_register()
1421 KBUILD_MODNAME, vin); in rvin_dma_register()
1423 vin_err(vin, "failed to request irq\n"); in rvin_dma_register()
1429 rvin_dma_unregister(vin); in rvin_dma_register()
1440 * as it's only possible to do so when no VIN in the group is
1443 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) in rvin_set_channel_routing() argument
1448 ret = pm_runtime_get_sync(vin->dev); in rvin_set_channel_routing()
1450 pm_runtime_put_noidle(vin->dev); in rvin_set_channel_routing()
1455 vnmc = rvin_read(vin, VNMC_REG); in rvin_set_channel_routing()
1456 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); in rvin_set_channel_routing()
1460 rvin_write(vin, ifmd, VNCSI_IFMD_REG); in rvin_set_channel_routing()
1462 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1465 rvin_write(vin, vnmc, VNMC_REG); in rvin_set_channel_routing()
1467 pm_runtime_put(vin->dev); in rvin_set_channel_routing()
1472 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha) in rvin_set_alpha() argument
1477 spin_lock_irqsave(&vin->qlock, flags); in rvin_set_alpha()
1479 vin->alpha = alpha; in rvin_set_alpha()
1481 if (vin->state == STOPPED) in rvin_set_alpha()
1484 switch (vin->format.pixelformat) { in rvin_set_alpha()
1486 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT; in rvin_set_alpha()
1487 if (vin->alpha) in rvin_set_alpha()
1491 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK; in rvin_set_alpha()
1492 dmr |= VNDMR_A8BIT(vin->alpha); in rvin_set_alpha()
1498 rvin_write(vin, dmr, VNDMR_REG); in rvin_set_alpha()
1500 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_set_alpha()