17 #define VFE_0_HW_VERSION		0x000
19 #define VFE_0_GLOBAL_RESET_CMD		0x018
20 #define VFE_0_GLOBAL_RESET_CMD_CORE	BIT(0)
31 #define VFE_0_MODULE_LENS_EN		0x040
35 #define VFE_0_MODULE_ZOOM_EN		0x04c
40 #define VFE_0_CORE_CFG			0x050
41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR	0x4
42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB	0x5
43 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY	0x6
44 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY	0x7
47 #define VFE_0_IRQ_CMD			0x058
48 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR	BIT(0)
50 #define VFE_0_IRQ_MASK_0		0x05c
51 #define VFE_0_IRQ_MASK_0_CAMIF_SOF			BIT(0)
59 #define VFE_0_IRQ_MASK_1		0x060
60 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR			BIT(0)
66 #define VFE_0_IRQ_CLEAR_0		0x064
67 #define VFE_0_IRQ_CLEAR_1		0x068
69 #define VFE_0_IRQ_STATUS_0		0x06c
70 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF			BIT(0)
77 #define VFE_0_IRQ_STATUS_1		0x070
82 #define VFE_0_IRQ_COMPOSITE_MASK_0	0x074
83 #define VFE_0_VIOLATION_STATUS		0x07c
85 #define VFE_0_BUS_CMD			0x80
88 #define VFE_0_BUS_CFG			0x084
90 #define VFE_0_BUS_XBAR_CFG_x(x)		(0x90 + 0x4 * ((x) / 2))
93 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA		(0x1 << 4)
94 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER		(0x2 << 4)
95 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA	(0x3 << 4)
97 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA		0x0
98 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0	0xc
99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1	0xd
100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2	0xe
102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n)		(0x0a0 + 0x2c * (n))
103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT	0
104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n)	(0x0a4 + 0x2c * (n))
105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n)	(0x0ac + 0x2c * (n))
106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n)		(0x0b4 + 0x2c * (n))
109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK	(0x1f << 2)
110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n)		(0x0b8 + 0x2c * (n))
112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n)	(0x0bc + 0x2c * (n))
113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n)	(0x0c0 + 0x2c * (n))
115 							(0x0c4 + 0x2c * (n))
117 							(0x0c8 + 0x2c * (n))
118 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF	0xffffffff
120 #define VFE_0_BUS_PING_PONG_STATUS	0x338
122 #define VFE_0_BUS_BDG_CMD		0x400
125 #define VFE_0_BUS_BDG_QOS_CFG_0		0x404
126 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa9aaa9
127 #define VFE_0_BUS_BDG_QOS_CFG_1		0x408
128 #define VFE_0_BUS_BDG_QOS_CFG_2		0x40c
129 #define VFE_0_BUS_BDG_QOS_CFG_3		0x410
130 #define VFE_0_BUS_BDG_QOS_CFG_4		0x414
131 #define VFE_0_BUS_BDG_QOS_CFG_5		0x418
132 #define VFE_0_BUS_BDG_QOS_CFG_6		0x41c
133 #define VFE_0_BUS_BDG_QOS_CFG_7		0x420
134 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG	0x0001aaa9
136 #define VFE_0_BUS_BDG_DS_CFG_0		0x424
137 #define VFE_0_BUS_BDG_DS_CFG_0_CFG	0xcccc0011
138 #define VFE_0_BUS_BDG_DS_CFG_1		0x428
139 #define VFE_0_BUS_BDG_DS_CFG_2		0x42c
140 #define VFE_0_BUS_BDG_DS_CFG_3		0x430
141 #define VFE_0_BUS_BDG_DS_CFG_4		0x434
142 #define VFE_0_BUS_BDG_DS_CFG_5		0x438
143 #define VFE_0_BUS_BDG_DS_CFG_6		0x43c
144 #define VFE_0_BUS_BDG_DS_CFG_7		0x440
145 #define VFE_0_BUS_BDG_DS_CFG_8		0x444
146 #define VFE_0_BUS_BDG_DS_CFG_9		0x448
147 #define VFE_0_BUS_BDG_DS_CFG_10		0x44c
148 #define VFE_0_BUS_BDG_DS_CFG_11		0x450
149 #define VFE_0_BUS_BDG_DS_CFG_12		0x454
150 #define VFE_0_BUS_BDG_DS_CFG_13		0x458
151 #define VFE_0_BUS_BDG_DS_CFG_14		0x45c
152 #define VFE_0_BUS_BDG_DS_CFG_15		0x460
153 #define VFE_0_BUS_BDG_DS_CFG_16		0x464
154 #define VFE_0_BUS_BDG_DS_CFG_16_CFG	0x40000103
156 #define VFE_0_RDI_CFG_x(x)		(0x46c + (0x4 * (x)))
158 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK	(0xf << 28)
160 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK		(0xf << 4)
162 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS		0x3
164 #define VFE_0_CAMIF_CMD				0x478
165 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY	0
169 #define VFE_0_CAMIF_CFG				0x47c
171 #define VFE_0_CAMIF_FRAME_CFG			0x484
172 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG		0x488
173 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG		0x48c
174 #define VFE_0_CAMIF_SUBSAMPLE_CFG		0x490
175 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN	0x498
176 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN	0x49c
177 #define VFE_0_CAMIF_STATUS			0x4a4
180 #define VFE_0_REG_UPDATE		0x4ac
185 #define VFE_0_DEMUX_CFG				0x560
186 #define VFE_0_DEMUX_CFG_PERIOD			0x3
187 #define VFE_0_DEMUX_GAIN_0			0x564
188 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN		(0x80 << 0)
189 #define VFE_0_DEMUX_GAIN_0_CH0_ODD		(0x80 << 16)
190 #define VFE_0_DEMUX_GAIN_1			0x568
191 #define VFE_0_DEMUX_GAIN_1_CH1			(0x80 << 0)
192 #define VFE_0_DEMUX_GAIN_1_CH2			(0x80 << 16)
193 #define VFE_0_DEMUX_EVEN_CFG			0x574
194 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV	0x9cac
195 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU	0xac9c
196 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY	0xc9ca
197 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY	0xcac9
198 #define VFE_0_DEMUX_ODD_CFG			0x578
199 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV	0x9cac
200 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU	0xac9c
201 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY	0xc9ca
202 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY	0xcac9
204 #define VFE_0_SCALE_ENC_Y_CFG			0x91c
205 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE		0x920
206 #define VFE_0_SCALE_ENC_Y_H_PHASE		0x924
207 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE		0x934
208 #define VFE_0_SCALE_ENC_Y_V_PHASE		0x938
209 #define VFE_0_SCALE_ENC_CBCR_CFG		0x948
210 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE	0x94c
211 #define VFE_0_SCALE_ENC_CBCR_H_PHASE		0x950
212 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE	0x960
213 #define VFE_0_SCALE_ENC_CBCR_V_PHASE		0x964
215 #define VFE_0_CROP_ENC_Y_WIDTH			0x974
216 #define VFE_0_CROP_ENC_Y_HEIGHT			0x978
217 #define VFE_0_CROP_ENC_CBCR_WIDTH		0x97c
218 #define VFE_0_CROP_ENC_CBCR_HEIGHT		0x980
220 #define VFE_0_CLAMP_ENC_MAX_CFG			0x984
221 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0		(0xff << 0)
222 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1		(0xff << 8)
223 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2		(0xff << 16)
224 #define VFE_0_CLAMP_ENC_MIN_CFG			0x988
225 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0		(0x0 << 0)
226 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1		(0x0 << 8)
227 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2		(0x0 << 16)
229 #define VFE_0_REALIGN_BUF_CFG			0xaac
246 	dev_err(dev, "VFE HW Version = 0x%08x\n", hw_version);  in vfe_hw_version_read()
251 	if (vfe_id == 0)  in vfe_get_ub_size()
256 	return 0;  in vfe_get_ub_size()
299 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
326 	int val = 0;  in vfe_word_per_line_by_pixel()
359 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
367 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
388 		u16 width = 0, height = 0, bytesperline = 0, wpl;  in vfe_wm_line_based()
402 		reg = 0x3;  in vfe_wm_line_based()
409 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
411 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
474 	return (reg >> wm) & 0x1;  in vfe_wm_get_ping_pong_status()
480 		writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
482 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
491 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_connect_wm_to_rdi()
572 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
577 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
581 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
610 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
615 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
619 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
701 	u32 comp_mask = 0;  in vfe_enable_irq_pix_line()
708 	for (i = 0; i < output->wm_num; i++) {  in vfe_enable_irq_pix_line()
774 		return 0;  in vfe_calc_interp_reso()
793 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
815 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
963 	val = 0xffffffff;  in vfe_set_camif_cfg()
966 	val = 0xffffffff;  in vfe_set_camif_cfg()
969 	val = 0xffffffff;  in vfe_set_camif_cfg()
973 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);  in vfe_set_camif_cfg()
1021 	if (ret < 0)  in vfe_camif_wait_for_stop()
1043 	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);  in vfe_violation_read()
1061 	trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n",  in vfe_isr()
1084 	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)  in vfe_isr()
1087 			for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)  in vfe_isr()
1092 	for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++)  in vfe_isr()