Lines Matching refs:vfe
397 u8 vfe, u8 enable) in ispif_select_clk_mux() argument
404 val &= ~(0xf << (vfe * 8)); in ispif_select_clk_mux()
406 val |= (csid << (vfe * 8)); in ispif_select_clk_mux()
412 val &= ~(0xf << (vfe * 12)); in ispif_select_clk_mux()
414 val |= (csid << (vfe * 12)); in ispif_select_clk_mux()
420 val &= ~(0xf << (4 + (vfe * 8))); in ispif_select_clk_mux()
422 val |= (csid << (4 + (vfe * 8))); in ispif_select_clk_mux()
428 val &= ~(0xf << (4 + (vfe * 12))); in ispif_select_clk_mux()
430 val |= (csid << (4 + (vfe * 12))); in ispif_select_clk_mux()
436 val &= ~(0xf << (8 + (vfe * 12))); in ispif_select_clk_mux()
438 val |= (csid << (8 + (vfe * 12))); in ispif_select_clk_mux()
455 enum ispif_intf intf, u8 vfe) in ispif_validate_intf_status() argument
463 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0)); in ispif_validate_intf_status()
467 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0)); in ispif_validate_intf_status()
471 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1)); in ispif_validate_intf_status()
475 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1)); in ispif_validate_intf_status()
479 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2)); in ispif_validate_intf_status()
501 enum ispif_intf intf, u8 vfe) in ispif_wait_for_stop() argument
509 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0); in ispif_wait_for_stop()
512 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0); in ispif_wait_for_stop()
515 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1); in ispif_wait_for_stop()
518 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1); in ispif_wait_for_stop()
521 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2); in ispif_wait_for_stop()
546 u8 csid, u8 vfe, u8 enable) in ispif_select_csid() argument
550 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); in ispif_select_csid()
579 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); in ispif_select_csid()
591 u8 cid, u8 vfe, u8 enable) in ispif_select_cid() argument
599 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0); in ispif_select_cid()
602 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0); in ispif_select_cid()
605 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1); in ispif_select_cid()
608 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1); in ispif_select_cid()
611 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2); in ispif_select_cid()
632 u8 vfe, u8 enable) in ispif_config_irq() argument
638 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
642 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
644 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); in ispif_config_irq()
647 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
651 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
653 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); in ispif_config_irq()
656 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
660 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
662 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); in ispif_config_irq()
665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); in ispif_config_irq()
674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); in ispif_config_irq()
678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); in ispif_config_irq()
680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe)); in ispif_config_irq()
697 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable) in ispif_config_pack() argument
708 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0); in ispif_config_pack()
710 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0); in ispif_config_pack()
714 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1); in ispif_config_pack()
716 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1); in ispif_config_pack()
720 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2); in ispif_config_pack()
722 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2); in ispif_config_pack()
745 enum ispif_intf intf, u8 vfe, u8 vc) in ispif_set_intf_cmd() argument
750 val = &ispif->intf_cmd[vfe].cmd_1; in ispif_set_intf_cmd()
754 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); in ispif_set_intf_cmd()
757 val = &ispif->intf_cmd[vfe].cmd_0; in ispif_set_intf_cmd()
761 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); in ispif_set_intf_cmd()
781 u8 vfe = line->vfe_id; in ispif_set_stream() local
793 ispif_select_clk_mux(ispif, intf, csid, vfe, 1); in ispif_set_stream()
795 ret = ispif_validate_intf_status(ispif, intf, vfe); in ispif_set_stream()
801 ispif_select_csid(ispif, intf, csid, vfe, 1); in ispif_set_stream()
802 ispif_select_cid(ispif, intf, cid, vfe, 1); in ispif_set_stream()
803 ispif_config_irq(ispif, intf, vfe, 1); in ispif_set_stream()
807 intf, cid, vfe, 1); in ispif_set_stream()
809 intf, vfe, vc); in ispif_set_stream()
813 intf, vfe, vc); in ispif_set_stream()
816 ret = ispif_wait_for_stop(ispif, intf, vfe); in ispif_set_stream()
824 intf, cid, vfe, 0); in ispif_set_stream()
825 ispif_config_irq(ispif, intf, vfe, 0); in ispif_set_stream()
826 ispif_select_cid(ispif, intf, cid, vfe, 0); in ispif_set_stream()
827 ispif_select_csid(ispif, intf, csid, vfe, 0); in ispif_set_stream()
828 ispif_select_clk_mux(ispif, intf, csid, vfe, 0); in ispif_set_stream()