Lines Matching +full:avg +full:- +full:samples
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
14 #include <linux/clk-provider.h>
25 #include <linux/atmel-isc-media.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-image-sizes.h>
31 #include <media/v4l2-ioctl.h>
32 #include <media/v4l2-fwnode.h>
33 #include <media/v4l2-subdev.h>
34 #include <media/videobuf2-dma-contig.h>
36 #include "atmel-isc-regs.h"
37 #include "atmel-isc.h"
41 MODULE_PARM_DESC(debug, "debug level (0-2)");
46 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
181 /* 0 --> gamma 1/1.8 */
194 /* 1 --> gamma 1/2 */
207 /* 2 --> gamma 1/2.2 */
230 struct isc_ctrls *ctrls = &isc->ctrls; in isc_update_v4l2_ctrls()
233 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]); in isc_update_v4l2_ctrls()
234 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]); in isc_update_v4l2_ctrls()
235 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]); in isc_update_v4l2_ctrls()
236 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]); in isc_update_v4l2_ctrls()
238 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]); in isc_update_v4l2_ctrls()
239 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]); in isc_update_v4l2_ctrls()
240 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]); in isc_update_v4l2_ctrls()
241 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]); in isc_update_v4l2_ctrls()
246 struct isc_ctrls *ctrls = &isc->ctrls; in isc_update_awb_ctrls()
250 regmap_write(isc->regmap, ISC_WB_O_RGR, in isc_update_awb_ctrls()
251 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | in isc_update_awb_ctrls()
252 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); in isc_update_awb_ctrls()
253 regmap_write(isc->regmap, ISC_WB_O_BGB, in isc_update_awb_ctrls()
254 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | in isc_update_awb_ctrls()
255 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); in isc_update_awb_ctrls()
256 regmap_write(isc->regmap, ISC_WB_G_RGR, in isc_update_awb_ctrls()
257 ctrls->gain[ISC_HIS_CFG_MODE_R] | in isc_update_awb_ctrls()
258 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); in isc_update_awb_ctrls()
259 regmap_write(isc->regmap, ISC_WB_G_BGB, in isc_update_awb_ctrls()
260 ctrls->gain[ISC_HIS_CFG_MODE_B] | in isc_update_awb_ctrls()
261 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); in isc_update_awb_ctrls()
270 isc->ctrls.gain[c] = 1 << 9; in isc_reset_awb_ctrls()
272 isc->ctrls.offset[c] = 0; in isc_reset_awb_ctrls()
279 struct regmap *regmap = isc_clk->regmap; in isc_wait_clk_stable()
291 return -ETIMEDOUT; in isc_wait_clk_stable()
298 if (isc_clk->id == ISC_ISPCK) in isc_clk_prepare()
299 pm_runtime_get_sync(isc_clk->dev); in isc_clk_prepare()
310 if (isc_clk->id == ISC_ISPCK) in isc_clk_unprepare()
311 pm_runtime_put_sync(isc_clk->dev); in isc_clk_unprepare()
317 u32 id = isc_clk->id; in isc_clk_enable()
318 struct regmap *regmap = isc_clk->regmap; in isc_clk_enable()
322 dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n", in isc_clk_enable()
323 __func__, isc_clk->div, isc_clk->parent_id); in isc_clk_enable()
325 spin_lock_irqsave(&isc_clk->lock, flags); in isc_clk_enable()
328 (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | in isc_clk_enable()
329 (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id))); in isc_clk_enable()
332 spin_unlock_irqrestore(&isc_clk->lock, flags); in isc_clk_enable()
338 return -EINVAL; in isc_clk_enable()
344 u32 id = isc_clk->id; in isc_clk_disable()
347 spin_lock_irqsave(&isc_clk->lock, flags); in isc_clk_disable()
348 regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id)); in isc_clk_disable()
349 spin_unlock_irqrestore(&isc_clk->lock, flags); in isc_clk_disable()
357 if (isc_clk->id == ISC_ISPCK) in isc_clk_is_enabled()
358 pm_runtime_get_sync(isc_clk->dev); in isc_clk_is_enabled()
360 regmap_read(isc_clk->regmap, ISC_CLKSR, &status); in isc_clk_is_enabled()
362 if (isc_clk->id == ISC_ISPCK) in isc_clk_is_enabled()
363 pm_runtime_put_sync(isc_clk->dev); in isc_clk_is_enabled()
365 return status & ISC_CLK(isc_clk->id) ? 1 : 0; in isc_clk_is_enabled()
373 return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); in isc_clk_recalc_rate()
380 long best_rate = -EINVAL; in isc_clk_determine_rate()
381 int best_diff = -1; in isc_clk_determine_rate()
401 diff = abs(req->rate - rate); in isc_clk_determine_rate()
406 req->best_parent_rate = parent_rate; in isc_clk_determine_rate()
407 req->best_parent_hw = parent; in isc_clk_determine_rate()
410 if (!best_diff || rate < req->rate) in isc_clk_determine_rate()
418 dev_dbg(isc_clk->dev, in isc_clk_determine_rate()
421 __clk_get_name((req->best_parent_hw)->clk), in isc_clk_determine_rate()
422 req->best_parent_rate); in isc_clk_determine_rate()
427 req->rate = best_rate; in isc_clk_determine_rate()
437 return -EINVAL; in isc_clk_set_parent()
439 isc_clk->parent_id = index; in isc_clk_set_parent()
448 return isc_clk->parent_id; in isc_clk_get_parent()
459 return -EINVAL; in isc_clk_set_rate()
463 return -EINVAL; in isc_clk_set_rate()
465 isc_clk->div = div - 1; in isc_clk_set_rate()
485 struct regmap *regmap = isc->regmap; in isc_clk_register()
486 struct device_node *np = isc->dev->of_node; in isc_clk_register()
489 const char *clk_name = np->name; in isc_clk_register()
495 return -EINVAL; in isc_clk_register()
503 of_property_read_string(np, "clock-output-names", &clk_name); in isc_clk_register()
505 clk_name = "isc-ispck"; in isc_clk_register()
513 isc_clk = &isc->isc_clks[id]; in isc_clk_register()
514 isc_clk->hw.init = &init; in isc_clk_register()
515 isc_clk->regmap = regmap; in isc_clk_register()
516 isc_clk->id = id; in isc_clk_register()
517 isc_clk->dev = isc->dev; in isc_clk_register()
518 spin_lock_init(&isc_clk->lock); in isc_clk_register()
520 isc_clk->clk = clk_register(isc->dev, &isc_clk->hw); in isc_clk_register()
521 if (IS_ERR(isc_clk->clk)) { in isc_clk_register()
522 dev_err(isc->dev, "%s: clock register fail\n", clk_name); in isc_clk_register()
523 return PTR_ERR(isc_clk->clk); in isc_clk_register()
525 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk); in isc_clk_register()
535 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) in isc_clk_init()
536 isc->isc_clks[i].clk = ERR_PTR(-EINVAL); in isc_clk_init()
538 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { in isc_clk_init()
551 of_clk_del_provider(isc->dev->of_node); in isc_clk_cleanup()
553 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { in isc_clk_cleanup()
554 struct isc_clk *isc_clk = &isc->isc_clks[i]; in isc_clk_cleanup()
556 if (!IS_ERR(isc_clk->clk)) in isc_clk_cleanup()
557 clk_unregister(isc_clk->clk); in isc_clk_cleanup()
566 unsigned int size = isc->fmt.fmt.pix.sizeimage; in isc_queue_setup()
569 return sizes[0] < size ? -EINVAL : 0; in isc_queue_setup()
580 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); in isc_buffer_prepare()
581 unsigned long size = isc->fmt.fmt.pix.sizeimage; in isc_buffer_prepare()
584 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n", in isc_buffer_prepare()
586 return -EINVAL; in isc_buffer_prepare()
591 vbuf->field = isc->fmt.fmt.pix.field; in isc_buffer_prepare()
598 struct regmap *regmap = isc->regmap; in isc_start_dma()
599 u32 sizeimage = isc->fmt.fmt.pix.sizeimage; in isc_start_dma()
604 h = isc->fmt.fmt.pix.height; in isc_start_dma()
605 w = isc->fmt.fmt.pix.width; in isc_start_dma()
608 * In case the sensor is not RAW, it will output a pixel (12-16 bits) in isc_start_dma()
609 * with two samples on the ISC Data bus (which is 8-12) in isc_start_dma()
611 * by two, to get the real number of samples for the required pixels. in isc_start_dma()
613 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) { in isc_start_dma()
627 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK)); in isc_start_dma()
631 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK)); in isc_start_dma()
637 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); in isc_start_dma()
640 switch (isc->config.fourcc) { in isc_start_dma()
653 dctrl_dview = isc->config.dctrl_dview; in isc_start_dma()
656 spin_lock(&isc->awb_lock); in isc_start_dma()
658 spin_unlock(&isc->awb_lock); in isc_start_dma()
663 struct regmap *regmap = isc->regmap; in isc_set_pipeline()
664 struct isc_ctrls *ctrls = &isc->ctrls; in isc_set_pipeline()
669 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ in isc_set_pipeline()
672 regmap_field_write(isc->pipeline[i], val); in isc_set_pipeline()
678 bay_cfg = isc->config.sd_format->cfa_baycfg; in isc_set_pipeline()
686 gamma = &isc_gamma_table[ctrls->gamma_index][0]; in isc_set_pipeline()
699 regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); in isc_set_pipeline()
700 regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); in isc_set_pipeline()
705 struct regmap *regmap = isc->regmap; in isc_update_profile()
712 while ((sr & ISC_CTRL_UPPRO) && counter--) { in isc_update_profile()
718 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n"); in isc_update_profile()
719 return -ETIMEDOUT; in isc_update_profile()
727 struct regmap *regmap = isc->regmap; in isc_set_histogram()
728 struct isc_ctrls *ctrls = &isc->ctrls; in isc_set_histogram()
733 (isc->config.sd_format->cfa_baycfg in isc_set_histogram()
738 ctrls->hist_id = ISC_HIS_CFG_MODE_GR; in isc_set_histogram()
742 ctrls->hist_stat = HIST_ENABLED; in isc_set_histogram()
747 ctrls->hist_stat = HIST_DISABLED; in isc_set_histogram()
753 struct regmap *regmap = isc->regmap; in isc_configure()
755 struct isc_subdev_entity *subdev = isc->current_subdev; in isc_configure()
757 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; in isc_configure()
758 rlp_mode = isc->config.rlp_cfg_mode; in isc_configure()
759 pipeline = isc->config.bits_pipeline; in isc_configure()
761 dcfg = isc->config.dcfg_imode | in isc_configure()
764 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; in isc_configure()
784 if (isc->ctrls.awb && in isc_configure()
785 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_configure()
797 struct regmap *regmap = isc->regmap; in isc_start_streaming()
803 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1); in isc_start_streaming()
804 if (ret && ret != -ENOIOCTLCMD) { in isc_start_streaming()
805 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n", in isc_start_streaming()
810 pm_runtime_get_sync(isc->dev); in isc_start_streaming()
819 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_start_streaming()
821 isc->sequence = 0; in isc_start_streaming()
822 isc->stop = false; in isc_start_streaming()
823 reinit_completion(&isc->comp); in isc_start_streaming()
825 isc->cur_frm = list_first_entry(&isc->dma_queue, in isc_start_streaming()
827 list_del(&isc->cur_frm->list); in isc_start_streaming()
831 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_start_streaming()
833 /* if we streaming from RAW, we can do one-shot white balance adj */ in isc_start_streaming()
834 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_start_streaming()
835 v4l2_ctrl_activate(isc->do_wb_ctrl, true); in isc_start_streaming()
840 pm_runtime_put_sync(isc->dev); in isc_start_streaming()
842 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); in isc_start_streaming()
845 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_start_streaming()
846 list_for_each_entry(buf, &isc->dma_queue, list) in isc_start_streaming()
847 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); in isc_start_streaming()
848 INIT_LIST_HEAD(&isc->dma_queue); in isc_start_streaming()
849 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_start_streaming()
861 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_stop_streaming()
863 isc->stop = true; in isc_stop_streaming()
866 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) in isc_stop_streaming()
867 v4l2_err(&isc->v4l2_dev, in isc_stop_streaming()
871 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); in isc_stop_streaming()
873 pm_runtime_put_sync(isc->dev); in isc_stop_streaming()
876 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); in isc_stop_streaming()
877 if (ret && ret != -ENOIOCTLCMD) in isc_stop_streaming()
878 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n"); in isc_stop_streaming()
881 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_stop_streaming()
882 if (unlikely(isc->cur_frm)) { in isc_stop_streaming()
883 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf, in isc_stop_streaming()
885 isc->cur_frm = NULL; in isc_stop_streaming()
887 list_for_each_entry(buf, &isc->dma_queue, list) in isc_stop_streaming()
888 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); in isc_stop_streaming()
889 INIT_LIST_HEAD(&isc->dma_queue); in isc_stop_streaming()
890 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_stop_streaming()
897 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); in isc_buffer_queue()
900 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_buffer_queue()
901 if (!isc->cur_frm && list_empty(&isc->dma_queue) && in isc_buffer_queue()
902 vb2_is_streaming(vb->vb2_queue)) { in isc_buffer_queue()
903 isc->cur_frm = buf; in isc_buffer_queue()
906 list_add_tail(&buf->list, &isc->dma_queue); in isc_buffer_queue()
907 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_buffer_queue()
913 unsigned int num_formats = isc->num_user_formats; in find_format_by_fourcc()
918 fmt = isc->user_formats[i]; in find_format_by_fourcc()
919 if (fmt->fourcc == fourcc) in find_format_by_fourcc()
941 strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver)); in isc_querycap()
942 strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); in isc_querycap()
943 snprintf(cap->bus_info, sizeof(cap->bus_info), in isc_querycap()
944 "platform:%s", isc->v4l2_dev.name); in isc_querycap()
952 u32 index = f->index; in isc_enum_fmt_vid_cap()
956 f->pixelformat = controller_formats[index].fourcc; in isc_enum_fmt_vid_cap()
960 index -= ARRAY_SIZE(controller_formats); in isc_enum_fmt_vid_cap()
970 f->pixelformat = formats_list[i].fourcc; in isc_enum_fmt_vid_cap()
976 return -EINVAL; in isc_enum_fmt_vid_cap()
984 *fmt = isc->fmt; in isc_g_fmt_vid_cap()
999 switch (isc->try_config.fourcc) { in isc_try_validate_formats()
1038 ret = -EINVAL; in isc_try_validate_formats()
1040 v4l2_dbg(1, debug, &isc->v4l2_dev, in isc_try_validate_formats()
1045 if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) in isc_try_validate_formats()
1046 return -EINVAL; in isc_try_validate_formats()
1049 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) && in isc_try_validate_formats()
1050 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) in isc_try_validate_formats()
1051 return -EINVAL; in isc_try_validate_formats()
1063 switch (isc->try_config.fourcc) { in isc_try_configure_rlp_dma()
1068 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; in isc_try_configure_rlp_dma()
1069 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
1070 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1071 isc->try_config.bpp = 8; in isc_try_configure_rlp_dma()
1077 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10; in isc_try_configure_rlp_dma()
1078 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1079 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1080 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1086 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12; in isc_try_configure_rlp_dma()
1087 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1088 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1089 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1092 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; in isc_try_configure_rlp_dma()
1093 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1094 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1095 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1098 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; in isc_try_configure_rlp_dma()
1099 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1100 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1101 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1104 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; in isc_try_configure_rlp_dma()
1105 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1106 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1107 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1111 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32; in isc_try_configure_rlp_dma()
1112 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
1113 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1114 isc->try_config.bpp = 32; in isc_try_configure_rlp_dma()
1117 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; in isc_try_configure_rlp_dma()
1118 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; in isc_try_configure_rlp_dma()
1119 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; in isc_try_configure_rlp_dma()
1120 isc->try_config.bpp = 12; in isc_try_configure_rlp_dma()
1123 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; in isc_try_configure_rlp_dma()
1124 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; in isc_try_configure_rlp_dma()
1125 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; in isc_try_configure_rlp_dma()
1126 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1129 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; in isc_try_configure_rlp_dma()
1130 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
1131 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1132 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1135 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; in isc_try_configure_rlp_dma()
1136 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
1137 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1138 isc->try_config.bpp = 8; in isc_try_configure_rlp_dma()
1141 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; in isc_try_configure_rlp_dma()
1142 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
1143 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1144 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
1147 return -EINVAL; in isc_try_configure_rlp_dma()
1151 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; in isc_try_configure_rlp_dma()
1152 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
1153 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
1166 switch (isc->try_config.fourcc) { in isc_try_configure_pipeline()
1173 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
1174 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
1177 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1182 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
1183 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
1187 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1192 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
1193 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
1197 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1202 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
1203 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
1207 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1211 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
1213 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
1217 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1221 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
1236 if (!isc->try_config.sd_format) in isc_try_fse()
1239 fse.code = isc->try_config.sd_format->mbus_code; in isc_try_fse()
1242 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, in isc_try_fse()
1249 pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH; in isc_try_fse()
1250 pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT; in isc_try_fse()
1252 pad_cfg->try_crop.width = fse.max_width; in isc_try_fse()
1253 pad_cfg->try_crop.height = fse.max_height; in isc_try_fse()
1262 struct v4l2_pix_format *pixfmt = &f->fmt.pix; in isc_try_fmt()
1271 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) in isc_try_fmt()
1272 return -EINVAL; in isc_try_fmt()
1275 for (i = 0; i < isc->num_user_formats; i++) { in isc_try_fmt()
1276 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) { in isc_try_fmt()
1277 sd_fmt = isc->user_formats[i]; in isc_try_fmt()
1284 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat); in isc_try_fmt()
1307 sd_fmt = isc->user_formats[isc->num_user_formats - 1]; in isc_try_fmt()
1308 v4l2_dbg(1, debug, &isc->v4l2_dev, in isc_try_fmt()
1310 (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc); in isc_try_fmt()
1314 ret = -EINVAL; in isc_try_fmt()
1319 v4l2_dbg(1, debug, &isc->v4l2_dev, in isc_try_fmt()
1321 (char *)&sd_fmt->fourcc); in isc_try_fmt()
1324 isc->try_config.sd_format = sd_fmt; in isc_try_fmt()
1327 if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) in isc_try_fmt()
1328 pixfmt->width = ISC_MAX_SUPPORT_WIDTH; in isc_try_fmt()
1329 if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) in isc_try_fmt()
1330 pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; in isc_try_fmt()
1334 * The pixels will be transferred in this format Sensor -> ISC in isc_try_fmt()
1336 mbus_code = sd_fmt->mbus_code; in isc_try_fmt()
1342 isc->try_config.fourcc = pixfmt->pixelformat; in isc_try_fmt()
1345 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc; in isc_try_fmt()
1346 /* Re-try to validate the new format */ in isc_try_fmt()
1364 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt, in isc_try_fmt()
1371 pixfmt->field = V4L2_FIELD_NONE; in isc_try_fmt()
1372 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; in isc_try_fmt()
1373 pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; in isc_try_fmt()
1381 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n"); in isc_try_fmt()
1383 memset(&isc->try_config, 0, sizeof(isc->try_config)); in isc_try_fmt()
1400 v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code); in isc_set_fmt()
1401 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, in isc_set_fmt()
1406 isc->fmt = *f; in isc_set_fmt()
1408 if (isc->try_config.sd_format && isc->config.sd_format && in isc_set_fmt()
1409 isc->try_config.sd_format != isc->config.sd_format) { in isc_set_fmt()
1410 isc->ctrls.hist_stat = HIST_INIT; in isc_set_fmt()
1415 isc->config = isc->try_config; in isc_set_fmt()
1417 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n"); in isc_set_fmt()
1427 if (vb2_is_streaming(&isc->vb2_vidq)) in isc_s_fmt_vid_cap()
1428 return -EBUSY; in isc_s_fmt_vid_cap()
1444 if (inp->index != 0) in isc_enum_input()
1445 return -EINVAL; in isc_enum_input()
1447 inp->type = V4L2_INPUT_TYPE_CAMERA; in isc_enum_input()
1448 inp->std = 0; in isc_enum_input()
1449 strscpy(inp->name, "Camera", sizeof(inp->name)); in isc_enum_input()
1464 return -EINVAL; in isc_s_input()
1473 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a); in isc_g_parm()
1480 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a); in isc_s_parm()
1488 .code = isc->config.sd_format->mbus_code, in isc_enum_framesizes()
1489 .index = fsize->index, in isc_enum_framesizes()
1492 int ret = -EINVAL; in isc_enum_framesizes()
1495 for (i = 0; i < isc->num_user_formats; i++) in isc_enum_framesizes()
1496 if (isc->user_formats[i]->fourcc == fsize->pixel_format) in isc_enum_framesizes()
1500 if (controller_formats[i].fourcc == fsize->pixel_format) in isc_enum_framesizes()
1506 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, in isc_enum_framesizes()
1511 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; in isc_enum_framesizes()
1512 fsize->discrete.width = fse.max_width; in isc_enum_framesizes()
1513 fsize->discrete.height = fse.max_height; in isc_enum_framesizes()
1523 .code = isc->config.sd_format->mbus_code, in isc_enum_frameintervals()
1524 .index = fival->index, in isc_enum_frameintervals()
1525 .width = fival->width, in isc_enum_frameintervals()
1526 .height = fival->height, in isc_enum_frameintervals()
1529 int ret = -EINVAL; in isc_enum_frameintervals()
1532 for (i = 0; i < isc->num_user_formats; i++) in isc_enum_frameintervals()
1533 if (isc->user_formats[i]->fourcc == fival->pixel_format) in isc_enum_frameintervals()
1537 if (controller_formats[i].fourcc == fival->pixel_format) in isc_enum_frameintervals()
1543 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, in isc_enum_frameintervals()
1548 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; in isc_enum_frameintervals()
1549 fival->discrete = fie.interval; in isc_enum_frameintervals()
1588 struct v4l2_subdev *sd = isc->current_subdev->sd; in isc_open()
1591 if (mutex_lock_interruptible(&isc->lock)) in isc_open()
1592 return -ERESTARTSYS; in isc_open()
1602 if (ret < 0 && ret != -ENOIOCTLCMD) { in isc_open()
1607 ret = isc_set_fmt(isc, &isc->fmt); in isc_open()
1614 mutex_unlock(&isc->lock); in isc_open()
1621 struct v4l2_subdev *sd = isc->current_subdev->sd; in isc_release()
1625 mutex_lock(&isc->lock); in isc_release()
1634 mutex_unlock(&isc->lock); in isc_release()
1652 struct regmap *regmap = isc->regmap; in isc_interrupt()
1662 spin_lock(&isc->dma_queue_lock); in isc_interrupt()
1663 if (isc->cur_frm) { in isc_interrupt()
1664 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb; in isc_interrupt()
1665 struct vb2_buffer *vb = &vbuf->vb2_buf; in isc_interrupt()
1667 vb->timestamp = ktime_get_ns(); in isc_interrupt()
1668 vbuf->sequence = isc->sequence++; in isc_interrupt()
1670 isc->cur_frm = NULL; in isc_interrupt()
1673 if (!list_empty(&isc->dma_queue) && !isc->stop) { in isc_interrupt()
1674 isc->cur_frm = list_first_entry(&isc->dma_queue, in isc_interrupt()
1676 list_del(&isc->cur_frm->list); in isc_interrupt()
1681 if (isc->stop) in isc_interrupt()
1682 complete(&isc->comp); in isc_interrupt()
1685 spin_unlock(&isc->dma_queue_lock); in isc_interrupt()
1689 schedule_work(&isc->awb_work); in isc_interrupt()
1698 struct regmap *regmap = isc->regmap; in isc_hist_count()
1699 struct isc_ctrls *ctrls = &isc->ctrls; in isc_hist_count()
1700 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id]; in isc_hist_count()
1701 u32 *hist_entry = &ctrls->hist_entry[0]; in isc_hist_count()
1728 u32 *hist_count = &ctrls->hist_count[0]; in isc_wb_update()
1730 u64 avg = 0; in isc_wb_update() local
1740 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] + in isc_wb_update()
1742 avg >>= 1; in isc_wb_update()
1745 if (!avg) in isc_wb_update()
1754 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX]; in isc_wb_update()
1764 ctrls->offset[c] = (offset[c] - 1) << 3; in isc_wb_update()
1771 ctrls->offset[c] = -ctrls->offset[c]; in isc_wb_update()
1775 * divided by the actual range of color component (Max - Min) in isc_wb_update()
1782 (ctrls->hist_minmax[c][HIST_MAX_INDEX] - in isc_wb_update()
1783 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); in isc_wb_update()
1792 gw_gain[c] = div_u64(avg << 9, hist_count[c]); in isc_wb_update()
1797 ctrls->gain[c] = s_gain[c] * gw_gain[c]; in isc_wb_update()
1798 ctrls->gain[c] >>= 9; in isc_wb_update()
1806 struct regmap *regmap = isc->regmap; in isc_awb_work()
1807 struct isc_ctrls *ctrls = &isc->ctrls; in isc_awb_work()
1808 u32 hist_id = ctrls->hist_id; in isc_awb_work()
1814 if (isc->stop) in isc_awb_work()
1817 if (ctrls->hist_stat != HIST_ENABLED) in isc_awb_work()
1821 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; in isc_awb_work()
1822 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; in isc_awb_work()
1831 ctrls->hist_id = hist_id; in isc_awb_work()
1832 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; in isc_awb_work()
1834 pm_runtime_get_sync(isc->dev); in isc_awb_work()
1840 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) { in isc_awb_work()
1847 spin_lock_irqsave(&isc->awb_lock, flags); in isc_awb_work()
1849 spin_unlock_irqrestore(&isc->awb_lock, flags); in isc_awb_work()
1855 if (ctrls->awb == ISC_WB_ONETIME) { in isc_awb_work()
1856 v4l2_info(&isc->v4l2_dev, in isc_awb_work()
1857 "Completed one time white-balance adjustment.\n"); in isc_awb_work()
1860 ctrls->awb = ISC_WB_NONE; in isc_awb_work()
1866 if (ctrls->awb) in isc_awb_work()
1869 pm_runtime_put_sync(isc->dev); in isc_awb_work()
1874 struct isc_device *isc = container_of(ctrl->handler, in isc_s_ctrl()
1876 struct isc_ctrls *ctrls = &isc->ctrls; in isc_s_ctrl()
1878 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) in isc_s_ctrl()
1881 switch (ctrl->id) { in isc_s_ctrl()
1883 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; in isc_s_ctrl()
1886 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; in isc_s_ctrl()
1889 ctrls->gamma_index = ctrl->val; in isc_s_ctrl()
1892 return -EINVAL; in isc_s_ctrl()
1904 struct isc_device *isc = container_of(ctrl->handler, in isc_s_awb_ctrl()
1906 struct isc_ctrls *ctrls = &isc->ctrls; in isc_s_awb_ctrl()
1908 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) in isc_s_awb_ctrl()
1911 switch (ctrl->id) { in isc_s_awb_ctrl()
1913 if (ctrl->val == 1) in isc_s_awb_ctrl()
1914 ctrls->awb = ISC_WB_AUTO; in isc_s_awb_ctrl()
1916 ctrls->awb = ISC_WB_NONE; in isc_s_awb_ctrl()
1919 if (!isc->config.sd_format) in isc_s_awb_ctrl()
1923 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) in isc_s_awb_ctrl()
1924 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val; in isc_s_awb_ctrl()
1925 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new) in isc_s_awb_ctrl()
1926 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val; in isc_s_awb_ctrl()
1927 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new) in isc_s_awb_ctrl()
1928 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val; in isc_s_awb_ctrl()
1929 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new) in isc_s_awb_ctrl()
1930 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val; in isc_s_awb_ctrl()
1932 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new) in isc_s_awb_ctrl()
1933 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val; in isc_s_awb_ctrl()
1934 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new) in isc_s_awb_ctrl()
1935 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val; in isc_s_awb_ctrl()
1936 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new) in isc_s_awb_ctrl()
1937 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val; in isc_s_awb_ctrl()
1938 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) in isc_s_awb_ctrl()
1939 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val; in isc_s_awb_ctrl()
1943 if (vb2_is_streaming(&isc->vb2_vidq)) { in isc_s_awb_ctrl()
1955 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_s_awb_ctrl()
1959 if (ctrls->awb == ISC_WB_AUTO && in isc_s_awb_ctrl()
1960 vb2_is_streaming(&isc->vb2_vidq) && in isc_s_awb_ctrl()
1961 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_s_awb_ctrl()
1968 if (ctrls->awb == ISC_WB_NONE && in isc_s_awb_ctrl()
1969 ctrl->cluster[ISC_CTRL_DO_WB]->is_new && in isc_s_awb_ctrl()
1970 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags & in isc_s_awb_ctrl()
1972 ctrls->awb = ISC_WB_ONETIME; in isc_s_awb_ctrl()
1974 v4l2_dbg(1, debug, &isc->v4l2_dev, in isc_s_awb_ctrl()
1975 "One time white-balance started.\n"); in isc_s_awb_ctrl()
1984 struct isc_device *isc = container_of(ctrl->handler, in isc_g_volatile_awb_ctrl()
1986 struct isc_ctrls *ctrls = &isc->ctrls; in isc_g_volatile_awb_ctrl()
1988 switch (ctrl->id) { in isc_g_volatile_awb_ctrl()
1991 ctrl->cluster[ISC_CTRL_R_GAIN]->val = in isc_g_volatile_awb_ctrl()
1992 ctrls->gain[ISC_HIS_CFG_MODE_R]; in isc_g_volatile_awb_ctrl()
1993 ctrl->cluster[ISC_CTRL_B_GAIN]->val = in isc_g_volatile_awb_ctrl()
1994 ctrls->gain[ISC_HIS_CFG_MODE_B]; in isc_g_volatile_awb_ctrl()
1995 ctrl->cluster[ISC_CTRL_GR_GAIN]->val = in isc_g_volatile_awb_ctrl()
1996 ctrls->gain[ISC_HIS_CFG_MODE_GR]; in isc_g_volatile_awb_ctrl()
1997 ctrl->cluster[ISC_CTRL_GB_GAIN]->val = in isc_g_volatile_awb_ctrl()
1998 ctrls->gain[ISC_HIS_CFG_MODE_GB]; in isc_g_volatile_awb_ctrl()
2000 ctrl->cluster[ISC_CTRL_R_OFF]->val = in isc_g_volatile_awb_ctrl()
2001 ctrls->offset[ISC_HIS_CFG_MODE_R]; in isc_g_volatile_awb_ctrl()
2002 ctrl->cluster[ISC_CTRL_B_OFF]->val = in isc_g_volatile_awb_ctrl()
2003 ctrls->offset[ISC_HIS_CFG_MODE_B]; in isc_g_volatile_awb_ctrl()
2004 ctrl->cluster[ISC_CTRL_GR_OFF]->val = in isc_g_volatile_awb_ctrl()
2005 ctrls->offset[ISC_HIS_CFG_MODE_GR]; in isc_g_volatile_awb_ctrl()
2006 ctrl->cluster[ISC_CTRL_GB_OFF]->val = in isc_g_volatile_awb_ctrl()
2007 ctrls->offset[ISC_HIS_CFG_MODE_GB]; in isc_g_volatile_awb_ctrl()
2025 .min = -4095, \
2057 struct isc_ctrls *ctrls = &isc->ctrls; in isc_ctrl_init()
2058 struct v4l2_ctrl_handler *hdl = &ctrls->handler; in isc_ctrl_init()
2061 ctrls->hist_stat = HIST_INIT; in isc_ctrl_init()
2068 ctrls->brightness = 0; in isc_ctrl_init()
2069 ctrls->contrast = 256; in isc_ctrl_init()
2071 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); in isc_ctrl_init()
2072 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); in isc_ctrl_init()
2074 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, in isc_ctrl_init()
2079 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, in isc_ctrl_init()
2083 if (!isc->do_wb_ctrl) { in isc_ctrl_init()
2084 ret = hdl->error; in isc_ctrl_init()
2089 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_ctrl_init()
2091 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); in isc_ctrl_init()
2092 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); in isc_ctrl_init()
2093 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL); in isc_ctrl_init()
2094 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL); in isc_ctrl_init()
2095 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL); in isc_ctrl_init()
2096 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL); in isc_ctrl_init()
2097 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL); in isc_ctrl_init()
2098 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL); in isc_ctrl_init()
2104 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true); in isc_ctrl_init()
2115 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_bound()
2120 if (video_is_registered(&isc->video_dev)) { in isc_async_bound()
2121 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n"); in isc_async_bound()
2122 return -EBUSY; in isc_async_bound()
2125 subdev_entity->sd = subdev; in isc_async_bound()
2134 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_unbind()
2136 cancel_work_sync(&isc->awb_work); in isc_async_unbind()
2137 video_unregister_device(&isc->video_dev); in isc_async_unbind()
2138 v4l2_ctrl_handler_free(&isc->ctrls.handler); in isc_async_unbind()
2147 if (fmt->mbus_code == code) { in find_format_by_code()
2161 struct v4l2_subdev *subdev = isc->current_subdev->sd; in isc_formats_init()
2175 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", in isc_formats_init()
2180 fmt->sd_support = true; in isc_formats_init()
2185 return -ENXIO; in isc_formats_init()
2187 isc->num_user_formats = num_fmts; in isc_formats_init()
2188 isc->user_formats = devm_kcalloc(isc->dev, in isc_formats_init()
2189 num_fmts, sizeof(*isc->user_formats), in isc_formats_init()
2191 if (!isc->user_formats) in isc_formats_init()
2192 return -ENOMEM; in isc_formats_init()
2196 if (fmt->sd_support) in isc_formats_init()
2197 isc->user_formats[j++] = fmt; in isc_formats_init()
2212 .pixelformat = isc->user_formats[0]->fourcc, in isc_set_default_fmt()
2221 isc->fmt = f; in isc_set_default_fmt()
2227 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_complete()
2229 struct video_device *vdev = &isc->video_dev; in isc_async_complete()
2230 struct vb2_queue *q = &isc->vb2_vidq; in isc_async_complete()
2233 INIT_WORK(&isc->awb_work, isc_awb_work); in isc_async_complete()
2235 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); in isc_async_complete()
2237 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n"); in isc_async_complete()
2241 isc->current_subdev = container_of(notifier, in isc_async_complete()
2243 mutex_init(&isc->lock); in isc_async_complete()
2244 init_completion(&isc->comp); in isc_async_complete()
2247 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; in isc_async_complete()
2248 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; in isc_async_complete()
2249 q->drv_priv = isc; in isc_async_complete()
2250 q->buf_struct_size = sizeof(struct isc_buffer); in isc_async_complete()
2251 q->ops = &isc_vb2_ops; in isc_async_complete()
2252 q->mem_ops = &vb2_dma_contig_memops; in isc_async_complete()
2253 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; in isc_async_complete()
2254 q->lock = &isc->lock; in isc_async_complete()
2255 q->min_buffers_needed = 1; in isc_async_complete()
2256 q->dev = isc->dev; in isc_async_complete()
2260 v4l2_err(&isc->v4l2_dev, in isc_async_complete()
2266 INIT_LIST_HEAD(&isc->dma_queue); in isc_async_complete()
2267 spin_lock_init(&isc->dma_queue_lock); in isc_async_complete()
2268 spin_lock_init(&isc->awb_lock); in isc_async_complete()
2272 v4l2_err(&isc->v4l2_dev, in isc_async_complete()
2279 v4l2_err(&isc->v4l2_dev, "Could not set default format\n"); in isc_async_complete()
2285 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret); in isc_async_complete()
2290 strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name)); in isc_async_complete()
2291 vdev->release = video_device_release_empty; in isc_async_complete()
2292 vdev->fops = &isc_fops; in isc_async_complete()
2293 vdev->ioctl_ops = &isc_ioctl_ops; in isc_async_complete()
2294 vdev->v4l2_dev = &isc->v4l2_dev; in isc_async_complete()
2295 vdev->vfl_dir = VFL_DIR_RX; in isc_async_complete()
2296 vdev->queue = q; in isc_async_complete()
2297 vdev->lock = &isc->lock; in isc_async_complete()
2298 vdev->ctrl_handler = &isc->ctrls.handler; in isc_async_complete()
2299 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; in isc_async_complete()
2302 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); in isc_async_complete()
2304 v4l2_err(&isc->v4l2_dev, in isc_async_complete()
2312 mutex_destroy(&isc->lock); in isc_async_complete()
2326 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { in isc_subdev_cleanup()
2327 v4l2_async_notifier_unregister(&subdev_entity->notifier); in isc_subdev_cleanup()
2328 v4l2_async_notifier_cleanup(&subdev_entity->notifier); in isc_subdev_cleanup()
2331 INIT_LIST_HEAD(&isc->subdev_entities); in isc_subdev_cleanup()
2336 struct device *dev = isc->dev; in isc_pipeline_init()
2337 struct regmap *regmap = isc->regmap; in isc_pipeline_init()
2341 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ in isc_pipeline_init()
2361 isc->pipeline[i] = regs; in isc_pipeline_init()