38  * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver d…
384 static int cx23885_risc_decode(u32 risc)  in cx23885_risc_decode()  argument
415 	printk(KERN_DEBUG "0x%08x [ %s", risc,  in cx23885_risc_decode()
416 	       instr[risc >> 28] ? instr[risc >> 28] : "INVALID");  in cx23885_risc_decode()
418 		if (risc & (1 << (i + 12)))  in cx23885_risc_decode()
420 	pr_cont(" count=%d ]\n", risc & 0xfff);  in cx23885_risc_decode()
421 	return incr[risc >> 28] ? incr[risc >> 28] : 1;  in cx23885_risc_decode()
456 				      unsigned int bpl, u32 risc)  in cx23885_sram_channel_setup()  argument
499 		cx_write(ch->cmds_start + 0, risc);  in cx23885_sram_channel_setup()
530 		"init risc lo",  in cx23885_sram_channel_dump()
531 		"init risc hi",  in cx23885_sram_channel_dump()
536 		"risc pc lo",  in cx23885_sram_channel_dump()
537 		"risc pc hi",  in cx23885_sram_channel_dump()
545 	u32 risc;  in cx23885_sram_channel_dump()  local
556 		risc = cx_read(ch->cmds_start + 4 * (i + 14));  in cx23885_sram_channel_dump()
557 		pr_warn("%s:   risc%d: ", dev->name, i);  in cx23885_sram_channel_dump()
558 		cx23885_risc_decode(risc);  in cx23885_sram_channel_dump()
561 		risc = cx_read(ch->ctrl_start + 4 * i);  in cx23885_sram_channel_dump()
566 		n = cx23885_risc_decode(risc);  in cx23885_sram_channel_dump()
568 			risc = cx_read(ch->ctrl_start + 4 * (i + j));  in cx23885_sram_channel_dump()
570 				dev->name, i+j, risc, j);  in cx23885_sram_channel_dump()
589 				struct cx23885_riscmem *risc)  in cx23885_risc_disasm()  argument
594 	pr_info("%s: risc disasm: %p [dma=0x%08lx]\n",  in cx23885_risc_disasm()
595 	       dev->name, risc->cpu, (unsigned long)risc->dma);  in cx23885_risc_disasm()
596 	for (i = 0; i < (risc->size >> 2); i += n) {  in cx23885_risc_disasm()
598 		n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));  in cx23885_risc_disasm()
601 				dev->name, i + j, risc->cpu[i + j], j);  in cx23885_risc_disasm()
602 		if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))  in cx23885_risc_disasm()
633 	/* disable RISC controller */  in cx23885_shutdown()
737 	port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */  in cx23885_init_tsport()
738 	port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */  in cx23885_init_tsport()
1198 int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,  in cx23885_risc_buffer()  argument
1212 	/* estimate risc mem: worst case is one write per page border +  in cx23885_risc_buffer()
1220 	risc->size = instructions * 12;  in cx23885_risc_buffer()
1221 	risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);  in cx23885_risc_buffer()
1222 	if (risc->cpu == NULL)  in cx23885_risc_buffer()
1225 	/* write risc instructions */  in cx23885_risc_buffer()
1226 	rp = risc->cpu;  in cx23885_risc_buffer()
1235 	risc->jmp = rp;  in cx23885_risc_buffer()
1236 	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);  in cx23885_risc_buffer()
1241 				   struct cx23885_riscmem *risc,  in cx23885_risc_databuffer()  argument
1249 	/* estimate risc mem: worst case is one write per page border +  in cx23885_risc_databuffer()
1257 	risc->size = instructions * 12;  in cx23885_risc_databuffer()
1258 	risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);  in cx23885_risc_databuffer()
1259 	if (risc->cpu == NULL)  in cx23885_risc_databuffer()
1262 	/* write risc instructions */  in cx23885_risc_databuffer()
1263 	rp = risc->cpu;  in cx23885_risc_databuffer()
1268 	risc->jmp = rp;  in cx23885_risc_databuffer()
1269 	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);  in cx23885_risc_databuffer()
1273 int cx23885_risc_vbibuffer(struct pci_dev *pci, struct cx23885_riscmem *risc,  in cx23885_risc_vbibuffer()  argument
1287 	/* estimate risc mem: worst case is one write per page border +  in cx23885_risc_vbibuffer()
1295 	risc->size = instructions * 12;  in cx23885_risc_vbibuffer()
1296 	risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);  in cx23885_risc_vbibuffer()
1297 	if (risc->cpu == NULL)  in cx23885_risc_vbibuffer()
1299 	/* write risc instructions */  in cx23885_risc_vbibuffer()
1300 	rp = risc->cpu;  in cx23885_risc_vbibuffer()
1315 	risc->jmp = rp;  in cx23885_risc_vbibuffer()
1316 	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);  in cx23885_risc_vbibuffer()
1323 	struct cx23885_riscmem *risc = &buf->risc;  in cx23885_free_buffer()  local
1326 	pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);  in cx23885_free_buffer()
1406 	/* Stop the fifo and risc engine for this port */  in cx23885_start_dma()
1412 				   port->ts_packet_size, buf->risc.dma);  in cx23885_start_dma()
1416 		cx23885_risc_disasm(port, &buf->risc);  in cx23885_start_dma()
1510 	cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */  in cx23885_start_dma()
1585 	cx23885_risc_databuffer(dev->pci, &buf->risc,  in cx23885_buf_prepare()
1592  * The risc program for each buffer works as follows: it starts with a simple
1597  * This is the risc program of the first buffer to be queued if the active list
1619 	buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);  in cx23885_buf_queue()
1620 	buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);  in cx23885_buf_queue()
1621 	buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);  in cx23885_buf_queue()
1622 	buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */  in cx23885_buf_queue()
1630 		buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);  in cx23885_buf_queue()
1634 		prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);  in cx23885_buf_queue()
1657 			(unsigned long)buf->risc.dma);  in do_cancel_buffers()
1690 		pr_err("%s: V4L mpeg risc op code error, status = 0x%x\n",  in cx23885_irq_417()
1752 		pr_err("%s: mpeg risc op code error\n", dev->name);  in cx23885_irq_ts()