Lines Matching full:cx
87 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx) in load_cpu_fw_direct() argument
95 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { in load_cpu_fw_direct()
104 cx18_setup_page(cx, i); in load_cpu_fw_direct()
107 cx18_raw_writel(cx, *src, dst); in load_cpu_fw_direct()
108 if (cx18_raw_readl(cx, dst) != *src) { in load_cpu_fw_direct()
111 cx18_setup_page(cx, 0); in load_cpu_fw_direct()
118 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) in load_cpu_fw_direct()
122 cx18_setup_page(cx, SCB_OFFSET); in load_cpu_fw_direct()
126 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, in load_apu_fw_direct() argument
139 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { in load_apu_fw_direct()
142 cx18_setup_page(cx, 0); in load_apu_fw_direct()
173 cx18_setup_page(cx, seghdr.addr + i); in load_apu_fw_direct()
176 cx18_raw_writel(cx, src[(offset + j) / 4], in load_apu_fw_direct()
178 if (cx18_raw_readl(cx, dst + seghdr.addr + j) in load_apu_fw_direct()
183 cx18_setup_page(cx, 0); in load_apu_fw_direct()
190 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) in load_apu_fw_direct()
195 cx18_setup_page(cx, 0); in load_apu_fw_direct()
199 void cx18_halt_firmware(struct cx18 *cx) in cx18_halt_firmware() argument
202 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, in cx18_halt_firmware()
204 cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL, in cx18_halt_firmware()
208 void cx18_init_power(struct cx18 *cx, int lowpwr) in cx18_init_power() argument
212 cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN); in cx18_init_power()
215 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL, in cx18_init_power()
257 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT); in cx18_init_power()
258 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7, in cx18_init_power()
261 cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST); in cx18_init_power()
262 cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE); in cx18_init_power()
263 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH); in cx18_init_power()
268 cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT); in cx18_init_power()
269 cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F, in cx18_init_power()
271 cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST); in cx18_init_power()
275 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT); in cx18_init_power()
276 cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC); in cx18_init_power()
277 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST); in cx18_init_power()
295 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1, in cx18_init_power()
297 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2, in cx18_init_power()
301 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1, in cx18_init_power()
303 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2, in cx18_init_power()
307 cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1, in cx18_init_power()
309 cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2, in cx18_init_power()
311 cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1, in cx18_init_power()
313 cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2, in cx18_init_power()
317 void cx18_init_memory(struct cx18 *cx) in cx18_init_memory() argument
320 cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET, in cx18_init_memory()
324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
340 cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET, in cx18_init_memory()
345 cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG); in cx18_init_memory()
347 cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN, in cx18_init_memory()
350 cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7); in cx18_init_memory()
351 cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR); in cx18_init_memory()
353 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */ in cx18_init_memory()
354 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */ in cx18_init_memory()
355 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */ in cx18_init_memory()
356 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */ in cx18_init_memory()
357 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */ in cx18_init_memory()
358 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */ in cx18_init_memory()
359 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */ in cx18_init_memory()
360 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */ in cx18_init_memory()
361 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */ in cx18_init_memory()
362 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */ in cx18_init_memory()
368 int cx18_firmware_init(struct cx18 *cx) in cx18_firmware_init() argument
375 cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK); in cx18_firmware_init()
378 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, in cx18_firmware_init()
384 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) { in cx18_firmware_init()
389 cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU); in cx18_firmware_init()
390 cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); in cx18_firmware_init()
392 sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx); in cx18_firmware_init()
397 cx18_init_scb(cx); in cx18_firmware_init()
400 sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx, in cx18_firmware_init()
406 cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET, in cx18_firmware_init()
411 retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1; in cx18_firmware_init()
418 (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) { in cx18_firmware_init()
432 cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); in cx18_firmware_init()
435 sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0); in cx18_firmware_init()
440 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400); in cx18_firmware_init()