Lines Matching +full:5 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
125 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
126 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
127 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
128 #define DETECT_5V_B BIT(1) /* 5V present on input B */
129 #define DETECT_5V_A BIT(0) /* 5V present on input A */
132 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
133 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
134 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
135 #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */
148 #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */
149 #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */
150 #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */
151 #define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */
154 #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */
155 #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */
156 #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */
157 #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */
160 #define RT_MAN_CTRL_RT_AUTO BIT(7)
161 #define RT_MAN_CTRL_RT BIT(6)
162 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
163 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
166 #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */
167 #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */
168 #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */
169 #define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */
172 #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */
185 #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */
186 #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */
187 #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */
190 #define AUDIO_OUT_ENABLE_ACLK BIT(5)
191 #define AUDIO_OUT_ENABLE_WS BIT(4)
192 #define AUDIO_OUT_ENABLE_AP3 BIT(3)
193 #define AUDIO_OUT_ENABLE_AP2 BIT(2)
194 #define AUDIO_OUT_ENABLE_AP1 BIT(1)
195 #define AUDIO_OUT_ENABLE_AP0 BIT(0)
209 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
224 /* Page 0x01 - HDMI info and packets */
235 #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */
236 #define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */
237 #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */
238 #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */
239 #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */
240 #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */
241 #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */
242 #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */
244 /* Page 0x12 - HDMI Extra control and debug */
270 #define CLK_CFG_INV_OUT_CLK BIT(7)
271 #define CLK_CFG_INV_BUS_CLK BIT(6)
272 #define CLK_CFG_SEL_ACLK_EN BIT(1)
273 #define CLK_CFG_SEL_ACLK BIT(0)
276 /* Page 0x13 - HDMI Extra control and debug */
299 #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */
304 #define HDCP_DE_COMP_OR 5L
334 #define CGU_DBG_XO_FRO_SEL BIT(2)
335 #define CGU_DBG_VDP_CLK_SEL BIT(1)
336 #define CGU_DBG_PIX_CLK_SEL BIT(0)
339 #define MAN_DIS_OUT_BUF BIT(7)
340 #define MAN_DIS_ANA_PATH BIT(6)
341 #define MAN_DIS_HDCP BIT(5)
342 #define MAN_DIS_TMDS_ENC BIT(4)
343 #define MAN_DIS_TMDS_FLOW BIT(3)
344 #define MAN_RST_HDCP BIT(2)
345 #define MAN_RST_TMDS_ENC BIT(1)
346 #define MAN_RST_TMDS_FLOW BIT(0)
348 /* Page 0x14 - Audio Extra control and debug */
356 #define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */
363 #define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */
375 #define EDID_ENABLE_NACK_OFF BIT(7)
376 #define EDID_ENABLE_EDID_ONLY BIT(6)
377 #define EDID_ENABLE_B_EN BIT(1)
378 #define EDID_ENABLE_A_EN BIT(0)
385 #define HPD_POWER_EDID_ONLY BIT(1)
388 #define HPD_AUTO_READ_EDID BIT(7)
389 #define HPD_AUTO_HPD_F3TECH BIT(5)
390 #define HPD_AUTO_HP_OTHER BIT(4)
391 #define HPD_AUTO_HPD_UNSEL BIT(3)
392 #define HPD_AUTO_HPD_ALL_CH BIT(2)
393 #define HPD_AUTO_HPD_PRV_CH BIT(1)
394 #define HPD_AUTO_HPD_NEW_CH BIT(0)
396 /* Page 0x21 - EDID content */
406 /* Page 0x30 - NV Configuration */
426 /* Page 0x80 - CEC */
433 #define INTERRUPT_AFE BIT(7) /* AFE module */
434 #define INTERRUPT_HDCP BIT(6) /* HDCP module */
435 #define INTERRUPT_AUDIO BIT(5) /* Audio module */
436 #define INTERRUPT_INFO BIT(4) /* Infoframe module */
437 #define INTERRUPT_MODE BIT(3) /* HDMI mode module */
438 #define INTERRUPT_RATE BIT(2) /* rate module */
439 #define INTERRUPT_DDC BIT(1) /* DDC module */
440 #define INTERRUPT_SUS BIT(0) /* SUS module */
443 #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */
444 #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */
445 #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */
446 #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */
447 #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */
448 #define MASK_AKSV BIT(0) /* AKSV received (start of auth) */
451 #define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */
452 #define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */
453 #define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */
454 #define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */
455 #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */
456 #define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */
457 #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */
458 #define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */
461 #define MASK_MPT BIT(7) /* Config MTP end of process */
462 #define MASK_FMT BIT(5) /* Video format changed */
463 #define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */
464 #define MASK_SUS_END BIT(3) /* SUS last state reached */
465 #define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */
466 #define MASK_SUS_CH BIT(1) /* Selected input changed */
467 #define MASK_SUS_ST BIT(0) /* SUS state changed */
470 #define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */
471 #define MASK_DDC_ERR BIT(6) /* master DDC error */
472 #define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */
473 #define MASK_READ_DONE BIT(4) /* End of down EDID read */
474 #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */
475 #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */
476 #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */
477 #define MASK_DET_5V BIT(0) /* Detection of +5V */
480 #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
481 #define MASK_GAMUT BIT(6) /* Gamut packet */
482 #define MASK_ISRC2 BIT(5) /* ISRC2 packet */
483 #define MASK_ISRC1 BIT(4) /* ISRC1 packet */
484 #define MASK_ACP BIT(3) /* Audio Content Protection packet */
485 #define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */
486 #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */
487 #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */
490 #define MASK_MPS_IF BIT(6) /* MPEG Source Product */
491 #define MASK_AUD_IF BIT(5) /* Audio */
492 #define MASK_SPD_IF BIT(4) /* Source Product Descriptor */
493 #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */
494 #define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */
495 #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */
496 #define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */
499 #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */
500 #define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */
501 #define MASK_MUTE_FLG BIT(3) /* Audio Mute */
502 #define MASK_CH_STATE BIT(2) /* Channel status */
503 #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */
504 #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */
507 #define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */
508 #define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */
509 #define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */
510 #define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */
511 #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */
512 #define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */
513 #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */
514 #define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */
517 #define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */
518 #define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */
519 #define AUDCFG_BUS_SHIFT 5
525 #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */
532 #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */
533 #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */
537 #define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */
538 #define OF_BLK BIT(4) /* blanking codes */
539 #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */
542 #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
547 #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
559 #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
570 #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
581 #define RESET_DC BIT(7) /* Reset deep color module */
582 #define RESET_HDCP BIT(6) /* Reset HDCP module */
583 #define RESET_KSV BIT(5) /* Reset KSV-FIFO */
584 #define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */
585 #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */
586 #define RESET_PA BIT(2) /* Reset polarity adjust */
587 #define RESET_EP BIT(1) /* Reset Error protection */
588 #define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */
591 #define NACK_HDCP BIT(7) /* No ACK on HDCP request */
592 #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */
593 #define RESET_GAMUT BIT(3) /* Clear Gamut packet */
594 #define RESET_AI BIT(2) /* Clear ACP and ISRC packets */
595 #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */
596 #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */
599 #define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */
600 #define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */
601 #define HDCP_READY BIT(5) /* set by repeater function */
602 #define HDCP_FAST BIT(4) /* Up to 400kHz */
603 #define HDCP_11 BIT(1) /* HDCP 1.1 supported */
604 #define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */
607 #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */
608 #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */
609 #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */