Lines Matching +full:0 +full:x93
37 #define R_BYPASS 0x05 /* Bypass DSP */
38 #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
39 #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
40 #define QS 0x44 /* Quantization Scale Factor */
41 #define CTRLI 0x50
42 #define CTRLI_LP_DP 0x80
43 #define CTRLI_ROUND 0x40
44 #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
45 #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
46 #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
47 #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
48 #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
49 #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
50 #define XOFFL 0x53 /* OFFSET_X[7:0] */
51 #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
52 #define YOFFL 0x54 /* OFFSET_Y[7:0] */
53 #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
54 #define VHYX 0x55 /* Offset and size completion */
55 #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
56 #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
57 #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
58 #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
59 #define DPRP 0x56
60 #define TEST 0x57 /* Horizontal size completion */
61 #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
62 #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
63 #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
64 #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
65 #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
66 #define ZMHH 0x5C /* Zoom: Speed and H&W completion */
67 #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
68 #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
69 #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
70 #define BPADDR 0x7C /* SDE Indirect Register Access: Address */
71 #define BPDATA 0x7D /* SDE Indirect Register Access: Data */
72 #define CTRL2 0x86 /* DSP Module enable 2 */
73 #define CTRL2_DCW_EN 0x20
74 #define CTRL2_SDE_EN 0x10
75 #define CTRL2_UV_ADJ_EN 0x08
76 #define CTRL2_UV_AVG_EN 0x04
77 #define CTRL2_CMX_EN 0x01
78 #define CTRL3 0x87 /* DSP Module enable 3 */
79 #define CTRL3_BPC_EN 0x80
80 #define CTRL3_WPC_EN 0x40
81 #define SIZEL 0x8C /* Image Size Completion */
82 #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
83 #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
84 #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
85 #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
86 #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
87 #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
88 #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
89 #define CTRL0 0xC2 /* DSP Module enable 0 */
90 #define CTRL0_AEC_EN 0x80
91 #define CTRL0_AEC_SEL 0x40
92 #define CTRL0_STAT_SEL 0x20
93 #define CTRL0_VFIRST 0x10
94 #define CTRL0_YUV422 0x08
95 #define CTRL0_YUV_EN 0x04
96 #define CTRL0_RGB_EN 0x02
97 #define CTRL0_RAW_EN 0x01
98 #define CTRL1 0xC3 /* DSP Module enable 1 */
99 #define CTRL1_CIP 0x80
100 #define CTRL1_DMY 0x40
101 #define CTRL1_RAW_GMA 0x20
102 #define CTRL1_DG 0x10
103 #define CTRL1_AWB 0x08
104 #define CTRL1_AWB_GAIN 0x04
105 #define CTRL1_LENC 0x02
106 #define CTRL1_PRE 0x01
107 /* REG 0xC7 (unknown name): affects Auto White Balance (AWB)
108 * AWB_OFF 0x40
109 * AWB_SIMPLE 0x10
110 * AWB_ON 0x00 (Advanced AWB ?) */
111 #define R_DVP_SP 0xD3 /* DVP output speed control */
112 #define R_DVP_SP_AUTO_MODE 0x80
113 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
114 * = sysclk (48)/(2*[6:0]) (RAW);*/
115 #define IMAGE_MODE 0xDA /* Image Output Format Select */
116 #define IMAGE_MODE_Y8_DVP_EN 0x40
117 #define IMAGE_MODE_JPEG_EN 0x10
118 #define IMAGE_MODE_YUV422 0x00
119 #define IMAGE_MODE_RAW10 0x04 /* (DVP) */
120 #define IMAGE_MODE_RGB565 0x08
121 #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
122 * mode (0 for HREF is same as sensor) */
123 #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
124 * 1: Low byte first UYVY (C2[4] =0)
126 * 0: High byte first YUYV (C2[4]=0)
128 #define RESET 0xE0 /* Reset */
129 #define RESET_MICROC 0x40
130 #define RESET_SCCB 0x20
131 #define RESET_JPEG 0x10
132 #define RESET_DVP 0x04
133 #define RESET_IPU 0x02
134 #define RESET_CIF 0x01
135 #define REGED 0xED /* Register ED */
136 #define REGED_CLK_OUT_DIS 0x10
137 #define MS_SP 0xF0 /* SCCB Master Speed */
138 #define SS_ID 0xF7 /* SCCB Slave ID */
139 #define SS_CTRL 0xF8 /* SCCB Slave Control */
140 #define SS_CTRL_ADD_AUTO_INC 0x20
141 #define SS_CTRL_EN 0x08
142 #define SS_CTRL_DELAY_CLK 0x04
143 #define SS_CTRL_ACC_EN 0x02
144 #define SS_CTRL_SEN_PASS_THR 0x01
145 #define MC_BIST 0xF9 /* Microcontroller misc register */
146 #define MC_BIST_RESET 0x80 /* Microcontroller Reset */
147 #define MC_BIST_BOOT_ROM_SEL 0x40
148 #define MC_BIST_12KB_SEL 0x20
149 #define MC_BIST_12KB_MASK 0x30
150 #define MC_BIST_512KB_SEL 0x08
151 #define MC_BIST_512KB_MASK 0x0C
152 #define MC_BIST_BUSY_BIT_R 0x02
153 #define MC_BIST_MC_RES_ONE_SH_W 0x02
154 #define MC_BIST_LAUNCH 0x01
155 #define BANK_SEL 0xFF /* Register Bank Select */
156 #define BANK_SEL_DSP 0x00
157 #define BANK_SEL_SENS 0x01
163 #define GAIN 0x00 /* AGC - Gain control gain setting */
164 #define COM1 0x03 /* Common control 1 */
165 #define COM1_1_DUMMY_FR 0x40
166 #define COM1_3_DUMMY_FR 0x80
167 #define COM1_7_DUMMY_FR 0xC0
168 #define COM1_VWIN_LSB_UXGA 0x0F
169 #define COM1_VWIN_LSB_SVGA 0x0A
170 #define COM1_VWIN_LSB_CIF 0x06
171 #define REG04 0x04 /* Register 04 */
172 #define REG04_DEF 0x20 /* Always set */
173 #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
174 #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
175 #define REG04_VREF_EN 0x10
176 #define REG04_HREF_EN 0x08
177 #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
178 #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
179 #define COM2 0x09 /* Common control 2 */
180 #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
182 #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
183 #define PID 0x0A /* Product ID Number MSB */
184 #define VER 0x0B /* Product ID Number LSB */
185 #define COM3 0x0C /* Common control 3 */
186 #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
187 #define COM3_BAND_AUTO 0x02 /* Auto Banding */
188 #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
190 #define AEC 0x10 /* AEC[9:2] Exposure Value */
191 #define CLKRC 0x11 /* Internal clock */
192 #define CLKRC_EN 0x80
193 #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
194 #define COM7 0x12 /* Common control 7 */
195 #define COM7_SRST 0x80 /* Initiates system reset. All registers are
198 #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
199 #define COM7_RES_SVGA 0x40 /* SVGA */
200 #define COM7_RES_CIF 0x20 /* CIF */
201 #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
202 #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
203 #define COM8 0x13 /* Common control 8 */
204 #define COM8_DEF 0xC0
205 #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
206 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
207 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
208 #define COM9 0x14 /* Common control 9
210 #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
211 #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
212 #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
213 #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
214 #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
215 #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
216 #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
217 #define COM10 0x15 /* Common control 10 */
218 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
219 #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
222 * 0 otherwise. */
223 #define COM10_HREF_INV 0x08 /* Invert HREF polarity:
225 #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
226 #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
227 #define HEND 0x18 /* Horizontal Window end MSB 8 bit */
228 #define VSTART 0x19 /* Vertical Window start MSB 8 bit */
229 #define VEND 0x1A /* Vertical Window end MSB 8 bit */
230 #define MIDH 0x1C /* Manufacturer ID byte - high */
231 #define MIDL 0x1D /* Manufacturer ID byte - low */
232 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
233 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
234 #define VV 0x26 /* AGC/AEC Fast mode operating region */
235 #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
236 #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
237 #define REG2A 0x2A /* Dummy pixel insert MSB */
238 #define FRARL 0x2B /* Dummy pixel insert LSB */
239 #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
240 #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
241 #define YAVG 0x2F /* Y/G Channel Average value */
242 #define REG32 0x32 /* Common Control 32 */
243 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
244 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
245 #define ARCOM2 0x34 /* Zoom: Horizontal start point */
246 #define REG45 0x45 /* Register 45 */
247 #define FLL 0x46 /* Frame Length Adjustment LSBs */
248 #define FLH 0x47 /* Frame Length Adjustment MSBs */
249 #define COM19 0x48 /* Zoom: Vertical start point */
250 #define ZOOMS 0x49 /* Zoom: Vertical start point */
251 #define COM22 0x4B /* Flash light control */
252 #define COM25 0x4E /* For Banding operations */
253 #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */
254 #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */
255 #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6)
256 #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4)
257 #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
258 #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
259 #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
260 #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
261 #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */
262 #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */
263 #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */
264 #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4)
265 #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0)
266 #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
267 #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
268 #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
269 #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
270 #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
271 #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
276 #define MANUFACTURER_ID 0x7FA2
277 #define PID_OV2640 0x2642
278 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
318 #define ENDMARKER { 0xff, 0xff }
322 { 0x2c, 0xff },
323 { 0x2e, 0xdf },
325 { 0x3c, 0x32 },
330 { COM9, COM9_AGC_GAIN_8x | 0x08},
331 { 0x2c, 0x0c },
332 { 0x33, 0x78 },
333 { 0x3a, 0x33 },
334 { 0x3b, 0xfb },
335 { 0x3e, 0x00 },
336 { 0x43, 0x11 },
337 { 0x16, 0x10 },
338 { 0x39, 0x02 },
339 { 0x35, 0x88 },
340 { 0x22, 0x0a },
341 { 0x37, 0x40 },
342 { 0x23, 0x00 },
343 { ARCOM2, 0xa0 },
344 { 0x06, 0x02 },
345 { 0x06, 0x88 },
346 { 0x07, 0xc0 },
347 { 0x0d, 0xb7 },
348 { 0x0e, 0x01 },
349 { 0x4c, 0x00 },
350 { 0x4a, 0x81 },
351 { 0x21, 0x99 },
352 { AEW, 0x40 },
353 { AEB, 0x38 },
354 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
355 { 0x5c, 0x00 },
356 { 0x63, 0x00 },
357 { FLL, 0x22 },
358 { COM3, 0x38 | COM3_BAND_AUTO },
359 { REG5D, 0x55 },
360 { REG5E, 0x7d },
361 { REG5F, 0x7d },
362 { REG60, 0x55 },
363 { HISTO_LOW, 0x70 },
364 { HISTO_HIGH, 0x80 },
365 { 0x7c, 0x05 },
366 { 0x20, 0x80 },
367 { 0x28, 0x30 },
368 { 0x6c, 0x00 },
369 { 0x6d, 0x80 },
370 { 0x6e, 0x00 },
371 { 0x70, 0x02 },
372 { 0x71, 0x94 },
373 { 0x73, 0xc1 },
374 { 0x3d, 0x34 },
377 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */
378 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
379 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */
380 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */
381 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */
383 { 0xe5, 0x7f },
385 { 0x41, 0x24 },
387 { 0x76, 0xff },
388 { 0x33, 0xa0 },
389 { 0x42, 0x20 },
390 { 0x43, 0x18 },
391 { 0x4c, 0x00 },
392 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
393 { 0x88, 0x3f },
394 { 0xd7, 0x03 },
395 { 0xd9, 0x10 },
396 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 },
397 { 0xc8, 0x08 },
398 { 0xc9, 0x80 },
399 { BPADDR, 0x00 },
400 { BPDATA, 0x00 },
401 { BPADDR, 0x03 },
402 { BPDATA, 0x48 },
403 { BPDATA, 0x48 },
404 { BPADDR, 0x08 },
405 { BPDATA, 0x20 },
406 { BPDATA, 0x10 },
407 { BPDATA, 0x0e },
408 { 0x90, 0x00 },
409 { 0x91, 0x0e },
410 { 0x91, 0x1a },
411 { 0x91, 0x31 },
412 { 0x91, 0x5a },
413 { 0x91, 0x69 },
414 { 0x91, 0x75 },
415 { 0x91, 0x7e },
416 { 0x91, 0x88 },
417 { 0x91, 0x8f },
418 { 0x91, 0x96 },
419 { 0x91, 0xa3 },
420 { 0x91, 0xaf },
421 { 0x91, 0xc4 },
422 { 0x91, 0xd7 },
423 { 0x91, 0xe8 },
424 { 0x91, 0x20 },
425 { 0x92, 0x00 },
426 { 0x93, 0x06 },
427 { 0x93, 0xe3 },
428 { 0x93, 0x03 },
429 { 0x93, 0x03 },
430 { 0x93, 0x00 },
431 { 0x93, 0x02 },
432 { 0x93, 0x00 },
433 { 0x93, 0x00 },
434 { 0x93, 0x00 },
435 { 0x93, 0x00 },
436 { 0x93, 0x00 },
437 { 0x93, 0x00 },
438 { 0x93, 0x00 },
439 { 0x96, 0x00 },
440 { 0x97, 0x08 },
441 { 0x97, 0x19 },
442 { 0x97, 0x02 },
443 { 0x97, 0x0c },
444 { 0x97, 0x24 },
445 { 0x97, 0x30 },
446 { 0x97, 0x28 },
447 { 0x97, 0x26 },
448 { 0x97, 0x02 },
449 { 0x97, 0x98 },
450 { 0x97, 0x80 },
451 { 0x97, 0x00 },
452 { 0x97, 0x00 },
453 { 0xa4, 0x00 },
454 { 0xa8, 0x00 },
455 { 0xc5, 0x11 },
456 { 0xc6, 0x51 },
457 { 0xbf, 0x80 },
458 { 0xc7, 0x10 }, /* simple AWB */
459 { 0xb6, 0x66 },
460 { 0xb8, 0xA5 },
461 { 0xb7, 0x64 },
462 { 0xb9, 0x7C },
463 { 0xb3, 0xaf },
464 { 0xb4, 0x97 },
465 { 0xb5, 0xFF },
466 { 0xb0, 0xC5 },
467 { 0xb1, 0x94 },
468 { 0xb2, 0x0f },
469 { 0xc4, 0x5c },
470 { 0xa6, 0x00 },
471 { 0xa7, 0x20 },
472 { 0xa7, 0xd8 },
473 { 0xa7, 0x1b },
474 { 0xa7, 0x31 },
475 { 0xa7, 0x00 },
476 { 0xa7, 0x18 },
477 { 0xa7, 0x20 },
478 { 0xa7, 0xd8 },
479 { 0xa7, 0x19 },
480 { 0xa7, 0x31 },
481 { 0xa7, 0x00 },
482 { 0xa7, 0x18 },
483 { 0xa7, 0x20 },
484 { 0xa7, 0xd8 },
485 { 0xa7, 0x19 },
486 { 0xa7, 0x31 },
487 { 0xa7, 0x00 },
488 { 0xa7, 0x18 },
489 { 0x7f, 0x00 },
490 { 0xe5, 0x1f },
491 { 0xe1, 0x77 },
492 { 0xdd, 0x7f },
514 { XOFFL, XOFFL_SET(0) },
515 { YOFFL, YOFFL_SET(0) },
517 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
529 { RESET, 0x00}
547 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
557 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
558 { CTRLI, 0x00},
563 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
564 { CTRLI, 0x00},
570 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
571 { CTRLI, 0x00},
572 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
601 { 0xd7, 0x03 },
602 { 0x33, 0xa0 },
603 { 0xe5, 0x1f },
604 { 0xe1, 0x67 },
605 { RESET, 0x00 },
612 { 0xd7, 0x01 },
613 { 0x33, 0xa0 },
614 { 0xe1, 0x67 },
615 { RESET, 0x00 },
622 { 0xd7, 0x03 },
623 { RESET, 0x00 },
630 { 0xd7, 0x03 },
631 { RESET, 0x00 },
659 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { in ov2640_write_array()
662 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", in ov2640_write_array()
665 if (ret < 0) in ov2640_write_array()
669 return 0; in ov2640_write_array()
676 if (val < 0) in ov2640_mask_set()
682 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); in ov2640_mask_set()
731 return 0; in ov2640_s_ctrl()
734 if (ret < 0) in ov2640_s_ctrl()
739 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; in ov2640_s_ctrl()
744 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; in ov2640_s_ctrl()
747 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; in ov2640_s_ctrl()
762 if (reg->reg > 0xff) in ov2640_g_register()
766 if (ret < 0) in ov2640_g_register()
771 return 0; in ov2640_g_register()
779 if (reg->reg > 0xff || in ov2640_s_register()
780 reg->val > 0xff) in ov2640_s_register()
796 gpiod_set_value(priv->resetb_gpio, 0); in ov2640_set_power()
809 * If the power count is modified from 0 to != 0 or from != 0 to 0, in ov2640_s_power()
815 WARN_ON(priv->power_count < 0); in ov2640_s_power()
818 return 0; in ov2640_s_power()
826 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { in ov2640_select_win()
876 if (ret < 0) in ov2640_set_params()
882 if (ret < 0) in ov2640_set_params()
887 if (ret < 0) in ov2640_set_params()
893 if (ret < 0) in ov2640_set_params()
898 if (ret < 0) in ov2640_set_params()
901 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; in ov2640_set_params()
903 if (ret < 0) in ov2640_set_params()
906 return 0; in ov2640_set_params()
928 mf = v4l2_subdev_get_try_format(sd, cfg, 0); in ov2640_get_fmt()
930 return 0; in ov2640_get_fmt()
945 return 0; in ov2640_get_fmt()
956 int ret = 0; in ov2640_set_fmt()
1012 v4l2_subdev_get_try_format(sd, cfg, 0); in ov2640_init_cfg()
1025 return 0; in ov2640_init_cfg()
1036 return 0; in ov2640_enum_mbus_code()
1049 sel->r.left = 0; in ov2640_get_selection()
1050 sel->r.top = 0; in ov2640_get_selection()
1053 return 0; in ov2640_get_selection()
1063 int ret = 0; in ov2640_s_stream()
1089 if (ret < 0) in ov2640_video_probe()
1113 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", in ov2640_video_probe()
1117 ov2640_s_power(&priv->subdev, 0); in ov2640_video_probe()
1187 return 0; in ov2640_probe_dt()
1232 V4L2_CID_VFLIP, 0, 1, 1, 0); in ov2640_probe()
1234 V4L2_CID_HFLIP, 0, 1, 1, 0); in ov2640_probe()
1237 ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0, in ov2640_probe()
1248 if (ret < 0) in ov2640_probe()
1253 if (ret < 0) in ov2640_probe()
1257 if (ret < 0) in ov2640_probe()
1262 return 0; in ov2640_probe()
1284 return 0; in ov2640_remove()
1288 { "ov2640", 0 },