Lines Matching refs:REG_AWB_AUTO
22 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
29 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
36 REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
43 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
50 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
57 REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
80 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
87 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
94 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
101 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
108 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
115 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
287 { V4L2_WHITE_BALANCE_AUTO, REG_AWB_AUTO }, in m5mols_set_white_balance()
302 ret = m5mols_write(sd, AWB_MODE, awb ? REG_AWB_AUTO : in m5mols_set_white_balance()