388 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,  in io_write_clr_set()  function
1111 	io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);  in set_rgb_quantization_range()
1118 			io_write_clr_set(sd, 0x02, 0xf0, 0x10);  in set_rgb_quantization_range()
1125 			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);  in set_rgb_quantization_range()
1132 			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);  in set_rgb_quantization_range()
1141 			io_write_clr_set(sd, 0x02, 0xf0, 0x00);  in set_rgb_quantization_range()
1144 			io_write_clr_set(sd, 0x02, 0xf0, 0x10);  in set_rgb_quantization_range()
1157 			io_write_clr_set(sd, 0x02, 0xf0, 0x20);  in set_rgb_quantization_range()
1165 		io_write_clr_set(sd, 0x02, 0xf0, 0x00);  in set_rgb_quantization_range()
1171 			io_write_clr_set(sd, 0x02, 0xf0, 0x60);  in set_rgb_quantization_range()
1179 		io_write_clr_set(sd, 0x02, 0xf0, 0x10);  in set_rgb_quantization_range()
1891 	io_write_clr_set(sd, 0x02, 0x02,  in adv76xx_setup_format()
1895 	io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));  in adv76xx_setup_format()
1896 	io_write_clr_set(sd, 0x05, 0x01,  in adv76xx_setup_format()
2079 		io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);  in adv76xx_cec_adap_enable()
2083 		io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);  in adv76xx_cec_adap_enable()
2807 	io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);  in adv76xx_core_init()
2808 	io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |  in adv76xx_core_init()
2843 		io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);  in adv76xx_core_init()